ST16C580
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 580 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Table 5, ST16C580 INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0
0
0
0
0
0
0
0
1
RHR [XX]
THR [XX]
IER [00]
bit-7
bit-7
bit-6
bit-6
bit-5
bit-5
bit-4
bit-4
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
CTS
interrupt
RTS
interrupt
Xoff
interrupt
Sleep
mode
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
FCR [00]
ISR [01]
LCR [00]
MCR [00]
LSR [60]
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
trigger
(MSB)
TX
trigger
(LSB)
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
FIFO’s
enabled
FIFO’s
enabled
INT
priority
bit-4
INT
priority
bit-3
INT
priority
bit-2
INT
priority
bit-1
INT
priority
bit-0
INT
status
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
Clock
select
IR
enable
0
loop
back
-OP2
-OP1
-RTS
-DTR
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
1
1
0
1
MSR [X0]
SPR [FF]
CD
RI
DSR
bit-5
CTS
bit-4
delta
-CD
delta
-RI
delta
-DSR
delta
-CTS
bit-7
bit-6
bit-3
bit-2
bit-1
bit-0
Special Register Set: Note *3
0
0
0
0
0
1
DLL[XX]
DLM[XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-9
bit-0
bit-8
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
Rev.1.20
16
EXAR [ EXAR CORPORATION ]
