DESCRꢁPTꢁꢀꢂ
Cꢀ is charged from Vcc to prepare it for its next
phase.
Wake-Up Feature for the SP312E
The SP3ꢀ2E has a wake-up feature that keeps
the receivers active when the device is placed
into shutdown. Table 1 defines the truth table for
the Wake-Up function. When only the receivers
are activated, the SP3ꢀ2E typically draws less
than 5uA supply current. In the case of when
a modem is interfaced to a computer in power
down mode, the Ring Indicator (RI) signal from
the modem would be used to "wake-up" the
computer, allowing it to accept data transmis-
sion.
Phase 3
Vdd charge store and double: Phase three is
identical to the first phase. The positive termi-
nals of Cꢀ and C2 are charged from Vcc with
their negative terminals initially connected to
ground. Cꢀ+ is then connected to ground and
the stored charge from Cꢀ- is superimposed
onto C2-. Since C2+ is still connected to Vcc
the voltage potential across capacitor C2 is now
2 x Vcc.
After the ring indicator has propagated
through the SP3ꢀ2E receiver, it can be used
to trigger the power management circuitry of
the computer to power up the microproces-
sor, and bring the SD pin of the SP3ꢀ2E to a
logic high, taking it out of the shutdown mode.
The receiver propagation delay is typically
ꢀus. The enable time for V+ and V- is typi-
cally 2ms. After V+ and V- have settled to their
final values, a signal can be sent back to the
modem on the data terminal ready (DTR) pin
signifying that the computer is ready to accept
the transmit data.
Phase 4
Vdd transfer: The fourth phase connects the
negative terminal of C2 to ground and the posi-
tive terminal of C2 to the Vdd storage capacitor.
This transfers the doubled (V+) voltage onto C3.
Meanwhile, capacitor Cꢀ is charged from Vcc to
prepare it for its next phase.
The clock rate for the charge pump typically op-
erates at greater than ꢀ5kHz allowing the pump
to run efficiently with small 0.1uF capacitors. Ef-
ficient operation depends on rapid charging and
discharging of Cꢀ and C2, therefore capacitors
should be mounted as close as possible to the
IC and have low ESR (equivalent series resis-
tance). Inexpensive surface mount, ceramic ca-
pacitors are ideal for using on charge pump. If
polarized capacitors are used the positive and
negative terminals should be connected as
shown in the typical operating circuit. A diagram
of the individual phases are shown in Figure ꢀ.
Power
Receiver
SD EN Up/Down outputs
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
Down
Down
Up
Enabled
Tri-state
Enabled
Tri-state
Up
Table ꢀ. Wake-up Function truth table
Shutdown (SD) and Enaꢅle (Eꢂ) features for
the SP310E and SP312E
Pin Strapping for the SP233E
To operate properly, the following pairs of pins
must be externally wired together as noted in
table 2:
Both the SP3ꢀ0E and SP3ꢀ2E have a shutdown
/ standby mode to conserve power in battery-
powered applications. To activate the shutdown
mode, which stops the operation of the charge
pump, a logic "0" is applied to the appropriate
control line. For the SP3ꢀ0E, this control line is
the ON/OFF (pin ꢀ8) input. Activating the shut-
down mode puts the SP3ꢀ0E transmitter and
receiver ouptuts into a high impedance con-
dition. For the SP3ꢀ2E, this control line is the
SHUTDOWN (pinꢀ8) input; this also puts the
transmitter outputs in a tri-state mode. The re-
ceiver outputs can be tri-stated seperately dur-
ing normal operation or shutdown by applying a
logic "ꢀ" on the EN line (pin ꢀ).
Pins Wired
Together
SOICW
Two V- pins
Two C2+ pins
Two C- pins
ꢀ0 & ꢀ7
ꢀ2 & ꢀ5
ꢀꢀ & ꢀ6
Connect Pins 6 and 9 to
GND
Table 2. Pin Strapping table for SP233E
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (5ꢀ0)668-7000 • www.exar.com SP202E,232E,233E, 3ꢀ0E, 3ꢀ2E_ꢀ00_ꢀꢀ0608
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