DESCRꢀPTꢀoꢁ
Phase 4
After the ring indicator has propagated
Vdd transfer: The fourth phase connects the
negative terminal of C2 to ground and the posi-
tive terminal of C2 to the Vdd storage capacitor.
This transfers the doubled (V+) voltage onto C3.
Meanwhile, capacitor Cꢀ is charged from Vcc to
prepare it for its next phase.
through the SP3ꢀ2A receiver, it can be used
to trigger the power management circuitry of
the computer to power up the microproces-
sor, and bring the SD pin of the SP3ꢀ2A to a
logic high, taking it out of the shutdown mode.
The receiver propagation delay is typically
ꢀus. The enable time for V+ and V- is typi-
cally 2ms. After V+ and V- have settled to their
final values, a signal can be sent back to the
modem on the data terminal ready (DTR) pin
signifying that the computer is ready to accept
the transmit data.
The clock rate for the charge pump typically op-
erates at greater than ꢀ5kHz allowing the pump
to run efficiently with small 0.1uF capacitors. Ef-
ficient operation depends on rapid charging and
discharging of Cꢀ and C2, therefore capacitors
should be mounted as close as possible to the
IC and have low ESR (equivalent series resis-
tance). Inexpensive surface mount, ceramic ca-
pacitors are ideal for using on charge pump. If
polarized capacitors are used the positive and
negative terminals should be connected as
shown in the typical operating circuit. A diagram
of the individual phases are shown in Figure ꢀ.
Power
Receiver
SD EN Up/Down outputs
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
Down
Down
Up
Enabled
Tri-state
Enabled
Tri-state
Up
Shutdꢂwn (SD) and Enaꢄle (Eꢁ) features fꢂr
the SP310A and SP312A
Table ꢀ. Wake-up Function truth table
Both the SP3ꢀ0A and SP3ꢀ2A have a shutdown
/ standby mode to conserve power in battery-
powered applications. To activate the shutdown
mode, which stops the operation of the charge
pump, a logic "0" is applied to the appropriate
control line. For the SP3ꢀ0A, this control line is
the ON/OFF (pin ꢀ8) input. Activating the shut-
down mode puts the SP3ꢀ0A transmitter and re-
ceiver ouptuts into a high impedance condition.
For the SP3ꢀ2A, this control line is the SHUT-
DOWN (pinꢀ8) input; this also puts the transmit-
ter outputs in a tri-state mode. The receiver out-
puts can be tri-stated seperately during normal
operation or shutdown by applying a logic "ꢀ" on
the EN line (pin ꢀ).
Pin Strappinꢃ fꢂr the SP233ACT/ACP
The SP233A packaged in a 20 pin SOICW
package (SP233ACT) has a slightly different
pinout than the SP233A in PDIP packaging
(SP233ACP). To operate properly, the fol-
lowing pairs of pins must be externally wired
together as noted in table 2:
Pins Wired
Together
SOICW
ꢀ0 & ꢀ7
PDIP
Two V- pins
ꢀ2 & ꢀ7
ꢀꢀ & ꢀ5
ꢀ0 & ꢀ6
Two C2+ pins ꢀ2 & ꢀ5
Two C- pins ꢀꢀ & ꢀ6
Wake-Up Feature fꢂr the SP312A
The SP3ꢀ2A has a wake-up feature that keeps
the receivers active when the device is placed
into shutdown. Table 1 defines the truth table for
the Wake-Up function. When only the receivers
are activated, the SP3ꢀ2A typically draws less
than 5uA supply current. In the case of when
a modem is interfaced to a computer in power
down mode, the Ring Indicator (RI) signal from
the modem would be used to "wake-up" the
computer, allowing it to accept data transmis-
sion.
No Connections for
Pins 8, ꢀ3 and ꢀ4
Connect Pins 6 and 9
to GND
Table 2. Pin Strapping table for SP233A
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (5ꢀ0)668-7000 • Fax (5ꢀ0)668-70ꢀ7 • www.exar.com SP233A,3ꢀ0A,3ꢀ2A ꢀ00_05ꢀ308
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