XRP7724
Quad Channel Digital PWM/PFM
Programmable Power Management System
PIN ASSIGNMENT
LDO3_3
1
2
33
32
31
30
29
28
27
26
25
24
23
GL_RTN2
GL2
AGND
CPLL
3
LX2
AVDD
VOUT1
VOUT2
VOUT3
VOUT4
GPIO0
GPIO1
SDA
4
GH2
5
BST2
GL_RTN3
GL3
XRP7724
TQFN
7mm X 7mm
6
7
8
LX3
9
GH3
Exposed Pad: AGND
10
11
BST3
VCCD3-4
Fig. 4: XRP7724 Pin Assignment
PIN DESCRIPTION
Name
Pin Number
Description
Input voltage. Place a decoupling capacitor close to the controller IC. This input is used
in UVLO fault generation.
41
16
VCC
1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling
capacitor close to the controller IC.
DVDD
Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies
drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be
connected to the LDO5 pin to enable two power rails initially. It is recommended that
the other VCCD pin be connected to the output of a 5V switching rail(for improved
efficiency or for driving larger external FETs), if available, otherwise this pin may also
be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for
each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch.
VCCD1-2
VCCD3-4
23,34
2
Analog ground pin. This is the small signal ground connection.
AGND
Ground connection for the low side gate driver. This should be routed as a signal trace
with GL. Connect to the source of the low side MOSFET.
39,33, 28,22
38,32, 27,21
36,30, 25,19
GL_RTN1-4
Output pin of the low side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
GL1-GL4
GH1-GH4
Output pin of the high side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
© 2012 Exar Corporation
8/29
Rev. 1.0.1
EXAR [ EXAR CORPORATION ]
