FEATURES
THEORY OF OPERATION
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices provide four key
functions:
1. A battery backup switch for CMOS RAM,
CMOS microprocessors, or other logic.
2. Aresetoutputduringpower-up, power-down
and brownout conditions.
3. A reset pulse if the optional watchdog timer
has not been toggled within a specified time.
4. A 1.25V threshold detector for power-fail
warning, low battery detection, or to monitor a
power supply other than 3.3V or 3.0V.
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices are microprocessor
(µP)supervisorycircuitsthat monitorthepower
supplied to digital circuits such as microproces-
sors, microcontrollers, ormemory. Theseriesis
an ideal solution for portable, battery-powered
equipmentthatrequirespowersupplymonitoring.
Implementing this series will reduce the
number of components and overall complexity.
The watchdog functions of this product family
will continuously oversee the operational status
of a system.
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices differ in their reset-
voltage threshold levels and are ideally suited
for applications in automotive systems, intelligent
instruments,andbattery-poweredcomputersand
controllers. The series is a solid match for
designs where it is critical to monitor the
power supply to the µP and it’s related digital
components.
These µP supervisory circuits are not short-
circuit protected. Shorting VOUT to ground -
excluding power-up transients such as charging
a decoupling capacitor - may potentially damage
thesedevices.DecouplebothVCC andVBATTERY
pins to ground by placing 0.1µF capacitors as
close to the device as possible. The operational
features and benefits of the SP690T/S/R,
SP802T/S/R, SP804T/S/R and SP805T/S/R
devices are described in more detail below.
Reset Output
Regulated +3.3V or +3.0V
Unregulated
The microprocessor's (µP's) reset input starts
the µP in a known state. When the µP is in an
unknown state, it should be held in reset. The
SP690T/S/R, SP802T/S/R, SP804T/S/R and
SP805T/S/R devices assert reset during
power-up and prevent code execution errors
during power-down or brownout conditions.
0.1µF
DC
VCC
VCC
R
1
2
pin 7*
RESET
NMI
µP
PFI
PFO
WDI
VOUT
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
I/O LINE
R
RESET is guaranteed to be a logic LOW for 0V
<VCC <VRST,providedthatVBATTERY isgreater
than 1V. Without a backup battery, RESET is
guaranteed valid for VCC > 1V. Once VCC
exceeds the reset threshold, an internal timer
keeps RESET low for the reset timeout period.
After this period, RESET goes HIGH, as seen in
Figure 19.
VBATTERY
GND
BUS
GND
VCC
3.6V
Lithium
Battery
CMOS
RAM
0.1µF
GND
If a brownout condition occurs and VCC dips
below the reset threshold, RESET goes LOW.
Each time RESET is triggered, it stays low for
the reset timeout period. Any time VCC goes
below the reset threshold, the internal timer
restarts.
RESET for the SP690T/S/R and the SP802T/S/R
RESET for the SP804T/S/R and the SP805T/S/R
*
Figure 20. Typical Operating Circuit
SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
© 2006 Sipex Corporation
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