PINOUT
VOUT
1
2
3
4
8
7
6
5
VBATTERY
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
RESET / RESET*
WDI
VCC
GND
PFI
PFO
*SP804T/S/R and SP805T/S/R only
PIN ASSIGNMENTS
Pin 7 for SP690_/802_ only — Active-LOW
Reset Output. — Whenever RESET is
triggered by a watchdog timeout, it goes
LOW for 200ms. It stays LOW whenever
VCC is below the reset threshold and re-
mains LOW for 200ms after VCC rises
above the reset threshold or when the
watchdog triggers a reset.
Pin 1 —VOUT — Output Supply Voltage for
CMOS RAM. When VCC is above the
reset threshold, VOUT connects to VCC
through a P-channel MOSFET switch.
When VCC falls below the VSW and
VBATTERY, VBATTERY connects to VOUT
.
Connect to VCC if no battery is used.
Pin 2 — VCC — +5V Supply Input
Pin 7 for SP804_/805_ only — Active-HIGH
Pin 3 — GND — Ground reference for all
signals
Open-Drain Reset Output.
inverse operation of RESET.
—
The
Pin 4 — PFI — Power-Fail Comparator Input.
When PFI is less than 1.25V or when VCC
falls below the VSW, PFO goes LOW,
otherwise PFO remains HIGH. Connect
to GND if unused.
Pin 8 — VBATTERY — Backup-Battery Input.
WhenVCC fallsbelowVSW andVBATTERY
VOUT switchesfrom VCC to VBATTERY
,
.
WhenVCC risesabovetheresetthreshold,
VOUT reconnects to VCC. VBATTERY may
exceed VCC. Connect to VCC if no battery
is used.
Pin 5 — PFO — Power-Fail Comparator
Output. Leave open if unused.
Pin 6 — WDI — Watchdog Input. If WDI
remains HIGH or LOW for 1.6 seconds,
the internal watchdog timer triggers a
reset. The internal watchdog timer clears
when reset is asserted or WDI sees a
rising or falling edge. The watchdog
function cannot be disabled.
SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
© 2006 Sipex Corporation
6
EXAR [ EXAR CORPORATION ]
