XRP7724
Quad Channel Digital PWM/PFM
Programmable Power Management System
Name
Pin Number
Description
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching
node at the junction between the two external power MOSFETs and the inductor. These
pins are also used to measure voltage drop across bottom MOSFETs in order to provide
output current information to the control engine.
37,31, 26,20
LX1-LX4
High side driver supply pin(s). Connect BST to the external capacitor as shown in the
Typical Application Circuit on page 2. The high side driver is connected between the
BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each
cycle.
35,29, 24,18
9,10
BST1-BST4
GPI0-GPIO1
PSIO0-PSIO2
These pins can be configured as inputs or outputs to implement custom flags, power
good signals, enable/disable controls and synchronization to an external clock.
Open drain, these pins can be used to control external power MOSFETs to switch loads
on and off, shedding the load for fine grained power management. They can also be
configures as standard logic outputs or inputs just as any of the GPIOs can be
configured, but as open drains require an external pull-up when configured as outputs.
13,14,15
SMBus/I2C serial interface communication pins.
11,12
SDA, SCL
Connect to the output of the corresponding power stage. The output is sampled at least
once every switching cycle
5,6,7,8
VOUT1-VOUT4
Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of
the IC is in shutdown. This LDO is also used to power the internal Analog Blocks.
44
1
LDO5
Output of the 3.3V standby LDO. This is a micro power LDO that can remain active
while the rest of the IC is in shutdown.
LDO3_3
If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset,
registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be
placed into shutdown.
40
42
ENABLE
BFB
Input from the 15V output created by the external boost supply. When this pin goes
below a pre-defined threshold, a pulse is created on the low side drive to charge this
output back to the original level. If not used, this pin should be connected to GND.
Digital ground pin. This is the logic ground connection, and should be connected to the
ground plane close to the PAD.
17
3
DGND
CPLL
Connect to a 2.2nF capacitor to GND.
External 5V that can be provided. If one of the output channels is configured for 5V,
then this voltage can be fed back to this pin for reduced operating current of the chip
and improved efficiency.
43
V5EXT
Output of the internal 1.8V LDO. A decoupling capacitor should be placed between
AVDD and AGND close to the chip.
4
AVDD
PAD
This is the die attach paddle, which is exposed on the bottom of the part. Connect
externally to the ground plane.
45
ORDERING INFORMATION
Temperature
Part Number
Packing
Quantity
I2C Default
Address
Marking
Package
Note 1
Range
XRP7724ILB-F
Bulk
Halogen Free
Halogen Free
-40°C≤TJ≤+125°C
-40°C≤TJ≤+125°C
XRP7724ILB
YYWW X
0x28 (7Bit)
44-pin TQFN
XRP7724ILBTR-F
2.5K/Tape & Reel
Evaluation kit includes XRP7724EVB-DEMO-1 Evaluation Board with Power
Architect software and XRP77XXEVB-XCM (USB to I2C Exar Configuration Module)
XRP7724EVB-DEMO-2P-KIT
“YY” = Year – “WW” = Work Week – “X” = Lot Number; when applicable.
© 2012 Exar Corporation
9/29
Rev. 1.0.1
EXAR [ EXAR CORPORATION ]
