MP8820
clock phase φc. The voltage stored on the capacitor is then
equal to VBAL + (VIN – VTAP). This voltage will force the inverter
high or low and the result is latched.
t
MSU
t
WR
t
AP
φS
A
A
IN1
V
φS
φC
IN
φC
Latch
IN2
V
TAP
C1
A
IN8
Figure 6. Comparator Block Diagram
Figure 5. Analog Timing Diagram
Inside the ADC is a series of comparators that sample the
The analog to digital conversion happens in four phases.
During the first phase, the analog input is sampled. During the
second phase, this input is compared against the reference lad-
der to determine the MSBs. After the MSBs are determined, a
subrange is set for phase three, the conversion of the LSBs.
Once all the bits have been derived, the MP8820 performs a
correction. The valid data is then ready at the output. The timing
diagram is shown in Figure 7.
analog input and compare it against a resistor tap voltage. A
state machine generates the internal clocks necessary to con-
trol the comparators, φc (CLK high) and φs (CLK low = sample).
See Figure 6. The rising edge of the CLK input marks the end of
the sampling phase, φs. On φs, the analog input voltage is
sampled and stored across capacitor C1. The switches con-
trolled by φs are opened prior to the compare which is done on
Sample
φSN
φSN+1
Compare
MSBs
φCMSBs
Compare
LSBs
φCLSBs
Correction
Data
φCORR
Data Sample N-1
Data Sample N
Figure 7. Internal ADC Timing Diagram
The input mux operates as a standard 8 to 1 decoder. One of
eight analog inputs is selected depending on the condition of the
address pins A0, A1, and A2. The mux can change address af-
ter a time equal to tAP following the rising edge of WR. The ad-
dress should be held constant for at least 150 ns before the ris-
ing edge of WR.
Function
Start A tracking
WR
↓
XINT
1
A0
X
X
X
X
X
0
A1
X
X
X
X
X
0
A2
X
X
X
X
X
0
IN
Sample A
↑
1
IN
Start Convert
↑
1
Conversion Complete
Enable Output Data
1
↓
X
X
X
X
X
X
X
X
X
0
Select Input A
Select Input A
Select Input A
Select Input A
Select Input A
Select Input A
Select Input A
Select Input A
X
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
X
0
0
1
X
0
1
0
X
0
1
1
X
1
0
0
X
1
0
1
X
1
1
0
X
1
1
1
Table 2. Truth Table
Rev. 1.00
7
EXAR [ EXAR CORPORATION ]
