MP8820
curs in the negative half of the transfer function. Table 1. shows
the digital codes that result from different input voltages.
V
IN
+ Gain Error
+ INL Error
Ideal + Offset
Ideal
CODE
AIN
00000000
–FS
00000001
–FS + 1LSB
00000000
Actual
– INL Error
.
.
.
.
Offset
CODE
1111111
10000000
V
= BZ
MID
– Gain Error
.
.
.
.
11111110
11111111
FS – 2LSB
FS – 1LSB
Table 1. Digital Codes vs. Input Voltage
Figure 3. Transfer Characteristics
with Error Terms
TheMP8820usesastandaloneµPinterface. Theuserstarts
a conversion by taking WR low. While WR is low, the input track
and hold follows the input voltage, AIN. On the rising edge of
WR, theinputissampled. TherisingedgeofWRenablesastate
machine which steps the ADC through a conversion.
The sign of the digital output code is determined by whether
the input voltage, AIN, exceeds VMID. If AIN is greater than VMID
then the seven bit conversion occurs in the positive half of the
transfer function. If AIN is less than VMID, then the translation oc-
,
The output port is held in high impedance state during the
conversion period. The operating timing diagrams are shown in
Figure 4.
t
AP
t
WR
WR
Track A for Sample N
IN
t
CONV
T
IO
DB0-DB7
A0-A2
Data Valid for Sample N-1
Data Valid for Sample N
T
MSU
T
MH
Mux Address Valid
for Sample N
Figure 4. Operating Timing Diagrams
Analog To Digital Conversion
The MP8820 converts analog voltages into 256 digital codes
by encoding the outputs of 15 coarse and 15 fine comparators.
When WR goes low, the input sample and hold circuitry is en-
abled. The track and hold circuit will follow the output of the 8
channel mux. The channel that is to be converted does not need
to be selected until a time equal to TMSU, or 150 ns, before the
rising edge of WR. So, while WR is low, the track and hold circuit
only has to follow the analog input to be converted for 150 ns.
The analog input is sampled at a time equal to the aperture
delay, TAP, after the rising edge of WR. The aperture delay also
accounts for internal propagation delays. The mux address
linesmayalsoselectanewchannelatatimeequaltoTAP follow-
ing the rising edge of WR. For the analog timing diagram, see
Figure 5.
Rev. 1.00
6
EXAR [ EXAR CORPORATION ]
