MP8798
SIMPLIFIED BLOCK AND TIMING DIAGRAM
AV
DV
DD
DD
Coarse
Comparators
Adder
φ
S
φ
B
4
5
CLK
N
φ
B
OFW
V
V
REF(+)
DB9-DB0
OFW
N-1
N-1
N
N
Fine
Resolution
Com-
DB9-DB0
1/2 R
DFF
10
6
REF(–)
V
REF1(–)
parators
PD
Ladder
CLK
φ
S
A
IN1
A
IN2
A
IN3
A
IN4
1 or 4
MUX
WR
A1
Latch
2 to 4
Decoder
A0
4
AGND DGND
PIN CONFIGURATIONS
See Packaging Section for
Package Dimensions
1
28
1
2
3
4
5
28
27
26
25
24
DB3
DB4
DB5
DB6
DB7
DB2
DB3
DB4
DB5
DB6
DB7
DB2
2
3
27
26
25
24
23
22
21
20
19
18
17
16
15
DB1
DB0
PD
DB1
DB0
PD
AV
DD
AGND
4
5
AV
DD
6
6
7
23
22
DGND
AGND
DGND
7
DV
DV
A
IN4
A
IN4
DD
DD
8
8
21
20
19
18
17
16
15
WR
A1
A0
CLK
DB8
DB9
A
IN3
A
IN2
A
IN1
WR
A1
A0
CLK
DB8
DB9
A
IN3
A
IN2
A
IN1
9
9
10
11
12
13
14
10
11
12
13
14
1/2 R
1/2 R
V
V
V
V
V
V
REF1(–)
REF(–)
REF(+)
REF1(–)
REF(–)
REF(+)
OFW
OFW
28 Pin PDIP (0.300”)
NN28
28 Pin SOIC (Jedec, 0.300”) – S28
28 Pin SSOP – A28
Rev. 3.00
2
EXAR [ EXAR CORPORATION ]
