MP8798
t
R
t
F
when φS disconnects the latches from the comparators. Thisde-
lay is called aperture delay (tAP).
t
S
t
B
V
V
The coarse comparators make the first pass conversion and
selectsaladderrangeforthefinecomparators. Thefinecompa-
rators are connected to the selected range during the next φB
phase.
IH
CLOCK
IL
SAMPLE
N–1
AUTO
BALANCE
SAMPLE
N
AUTO
BALANCE
SAMPLE
N+1
TS
φB
φS
ANALOG
INPUT
φS
V
IN
Latch
V
OH
V
TAP
DATA
N-1
V
OL
Ref
Ladder
COARSE COMPARATOR
φB
φS
t
DL
φS
t
HLD
φB
V
IN
Figure 1. MP8798 Timing Diagram
Latch
V
TAP
THEORY OF OPERATION
Analog-to-Digital Conversion
FINE COMPARATOR
Selected
Range
φB
Figure 2. MP8798 Comparators
The MP8798 converts analog voltages into 1024 digital
codes by encoding the outputs of 15 coarse and 67 fine compa-
rators. Digital logic is used to generate the overflow bit. The con-
version is synchronous with the clock and it is accomplished in 2
clock periods.
A
IN
Sampling, Ladder Sampling, and Conversion Timing
Figure 3. shows this relationship as a timing chart. AIN sam-
pling, ladder sampling and output data relationships are shown
for the general case where the levels which drive the ladder
need to change for each sampled AIN time point. The ladder is
referenced for both last AIN sample and next AIN sample at the
same time. If the ladder’s levels change by more than 1 LSB,
one of the samples must be discarded. Also note that the clock
low period for the discarded AIN can be reduced to the minimum
tS time of 150 ns.
The reference resistance ladder is a series of 1025 resistors.
The first and the last resistor of the ladder are half the value of
the others so that the following relations apply:
RREF = 1024
R
VREF = VREF(+) – VREF(–) = 1024 LSB
The clock signal generates the two internal phases, φB (CLK
high) and φS (CLK low = sample) (See Figure 2.). The rising
edge of the CLK input marks the end of the sampling phase (φS).
Internal delay of the clock circuitry will delay the actual instant
Hold Reference Value Past
Short Cycle Sample will be discarded
Clock Change for t Time
AP
t
S
Settle by Clock Update Time
External
Reference Stable Time – For Sample A
2
IN
Update
Reference Stable Time – For Sample A
References
1
IN
A
X1
IN
Clock
Sample A
1
Sample A 2
IN
IN
Not Used F
B
F
Internal
Sample
Window
F
F
B
F
B
S
S
S
F
A
IN
A
X0
Sample A
1
A
X1
Sample A 2
IN
IN
IN
IN
Ladder Sample
Window (MSB Bank)
Sample Ladder
for A
Sample Ladder
Sample Ladder
for A
Sample Ladder
1
for A X1
2
IN
for A X2
IN
IN
IN
Ladder Compare
(LSB Bank)
Compare Ladder
Compare Ladder
Compare Ladder
Compare Ladder
V/S A X0
V/S A
1
V/S A X1
V/S A 2
IN
IN
IN
IN
External
DATA A
0
DATA A X0
IN
DATA A
1
DATA A X1
IN
DATA
IN
IN
Not Used
Not Used
Figure 3. A Sampling, Ladder Sampling & Conversion Timing
IN
Rev. 3.00
6
EXAR [ EXAR CORPORATION ]
