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MP8775AN 参数 Datasheet PDF下载

MP8775AN图片预览
型号: MP8775AN
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 20 MSPS , 8位高速模拟数字转换器 [CMOS 20 MSPS, 8-Bit, High Speed Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 8 页 / 460 K
品牌: EXAR [ EXAR CORPORATION ]
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MP8775
ELECTRICAL CHARACTERISTICS TABLE (CONT’D)
Description
AC PARAMETERS
Differential Gain Error
Differential Phase Error
POWER SUPPLIES
Operating Voltage (AV
DD
, DV
DD
)
9
Current (AV
DD
+ DV
DD
)
V
DD
I
DD
5
17
25
V
mA
Does not include ref. current
d
G
d
PH
2
1
%
°
FS = 4 x NTSC
FS = 4 x NTSC
Symbol
Min
25
°
C
Typ
Max
Units
Conditions
Notes:
1
Tester measures code transitions by dithering the voltage of the analog input (V
IN
). The difference between the measured and the
ideal code width (V
REF
/256) is the DNL error (Figure 2.). The INL error is the maximum distance (in LSBs) from the best fit line to
any transition voltage (Figure 3.). Accuracy is a function of the sampling rate (FS).
2
Guaranteed. Not tested.
3
Specified values guarantee functionality. Refer to other parameters for accuracy.
4
--1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within
the specified bandwidth.
5
See V
IN
input equivalent circuit (Figure 4.). Switched capacitor analog input requires driver with low output resistance.
6
All inputs have diodes to DV
DD
and DGND. Input DC currents will not exceed specified limits for any input voltage between
DGND and DV
DD
.
7
t
R
, t
F
should be limited to >5 ns for best results.
8
Depends on the RC load connected to the output pin.
9
AGND and DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C unless otherwise noted)
1, 2, 3
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
V
RT
& V
RB
. . . . . . . . . . . . . . . . . . . . V
DD
+0.5 to GND --0.5 V
V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+0.5 to GND --0.5 V
All Inputs . . . . . . . . . . . . . . . . . . . . . V
DD
+0.5 to GND --0.5 V
All Outputs . . . . . . . . . . . . . . . . . . . V
DD
+0.5 to GND --0.5 V
Storage Temperature . . . . . . . . . . . . . . . . . . . --65 to +150
°
C
Lead Temperature (Soldering 10 seconds) . . . . . . . +300
°
C
Package Power Dissipation Rating @ 75
°
C
SOIC, SSOP, PDIP . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Derates above 75
°
C . . . . . . . . . . . . . . . . . . . . . . 9 mW/°C
Notes:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100
m
s.
3
V
DD
refers to AV
DD
and DV
DD
. GND refers to AGND and DGND.
1/FS
t
PWH
t
PWL
CLK
Sample “N”
N+1
PIPELINE DELAY
N+2
DATA
N -- 3
N -- 2
N -- 1
DATA N
t
HL
t
DL
Figure 1. MP8775 Timing Diagram
Rev. 3.01
4