MP7680
INPUT
LA TCHES
DAC LA TCHES
DB11-DB4
(MSB)
DB11-
DB8
DB3-DB0
(LSB)
0
MUX
1
8
D
4
D
B1
E Latch
Q
LA11 - LA0
8
D
E
Q
DA11 - DA0
12
DAC
R
FBA
I
OUT1A
I
OUT2A
V
REFA
B2
Q 4
Latch
E
D
8
Q
B1
Latch
E
D
B2
Q 4
E Latch
D
Q
B1
E Latch
D
8
8
DB11 - DB0
12
D
E
DC11 - DC0
12
D
E
DD11 - DD0
12
D
E
Q
DAC
Q
DAC
Q
DAC
R
FBB
I
OUT1B
I
OUT2B
V
REFB
R
FBC
I
OUT1C
I
OUT2C
V
REFC
R
FBD
I
OUT1D
I
OUT2D
V
REFD
4
8
4
8
B1/B2
Disable-B1
4
Enable A
Latch
Address
Decoder
Enable B
Enable C
Enable D
B2
Q 4
Latch
E
D
D
Q
B1
Latch
E
8
B2
Q 4
E Latch
A1 (MSB)
A0 (LSB)
CS
WR1
Transfer
XFER WR2
Figure
3. Latches
Control
Logic
THEOR Y OF OPERA TION
Digital
Interface
W riting to Input Latches
Figure 3.
shows the internal control logic. The logic that
controls the writing of the input latches and the one that
controls the DAC latches are completely separated. It is
easy to understand how the MP7680/80A works by
understanding each basic operation.
By keeping B1/B2 = high, a 12-bit bus has direct access to
the 12 bits of the input latches. The condition CS = WR1 =
0 loads the values contained in the data bus DB11-DB0
into the input latch addresses by A
1
, A
0
(
Figure 4.
,
Table 1.
).
Rev. 3.10
8
EXAR [ EXAR CORPORATION ]
