MP7651
THEORY OF OPERATION
MP7651 is equipped with a serial data 3-wire standard
µ
-
processor logic interface to reduce pin count, package size (28
pin), and board wire (space). This interface consists of LD which
controls the transfer of data to the selected DAC channel, SDI
(serial data/address input), CLK (shift register clock) and SDO
(serial data output). When the LD signal is high, CLK signal
loads the digital input bits (SDI) into the 16-bit shift register (8 bits
data D7 to D0, plus 4 bits address A3 to A0, and 4 bits of Chip
Select data CS0S to CS3S). If the CS0S to CS3S in the shift reg-
ister match the parallel chip-select address (CS0P to CS3P) for
the selected chip, then the LD signal going low loads the data
Function
Shift Data In
and Out
Stop Shifting
Data In and
Out
Load DACs
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
A3 A2 A1 A0
X
X
X
X
X
X
X
X
LD
1
0
into the selected DAC of that chip. The LD signal going low also
disables the serial data input (SDI), output (SDO 3-stated) and
the CLK input. This design tremendously reduces digital noise,
and glitch transients into the DACs due to free running CLK and
SDI. Also, 3-stating the SDO output with LD signal would allow
read back of pre-stored digital data of the selected package us-
ing one SDO wire for all DAC ICs on the board. Note also that
the reset signal (RST) resets all analog outputs to 1/2 of V
REF
,
regardless of any digital inputs. Also note that the input V
Ri
is
referenced to GND.
CS0S CS1S CS2S CS3S
X
X
X
X
X
X
X
X
CLK
0
→
1
Repeat
RST
1
1
SDI
Data Input
X
SDO
Data Output
Hi-Z
X
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No Operation
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
No Operation
No Operation
No Operation
X
Matched with 4 parallel
chip select data
CS0P to CS3P
1
1
Reset all DACs X
to V
REF
/2
1
1
X
1
1
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
0
X
X
X
Hi-Z
Hi-Z
X
X
X
X
X
Table 1. Digital Function Truth Table
Serial In/Serial Out
D7
MSB
0
0
D6
D5
D4
D3
D2
D1
D0 DAC Output Voltage
D
LSB V
Oi
= AGND + (V
Ri –
AGND) (
256
)
0
1
AGND
1
(V
Ri
– AGND) ( 256 ) + AGND
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
254
(V
Ri
– AGND) ( 256 ) + AGND
255
(V
Ri
– AGND) ( 256 ) + AGND
Table 2. DAC Transfer Function
Analog Output vs. Digital Code
Rev. 2.00
7
EXAR [ EXAR CORPORATION ]
