MP7643
t
AS
A1, A0
t
DS
DB0 to DB7
LD
t
LD
t
SD
V
OUT
1/2
LSB
t
DH
t
AH
1/2
LSB
Figure 1. Timing Diagram
To DAC1 Latch Enable
2-4
Decoder
To DAC2 Latch Enable
To DAC3 Latch Enable
To DAC4 Latch Enable
LD
L
↑
L
↑
L
↑
L
↑
H
A1
L
L
L
L
H
H
H
H
X
A0
L
L
H
H
L
L
H
H
X
Operation
DAC1 Transparent
DAC1 Latched
DAC2 Transparent
DAC2 Latched
DAC3 Transparent
DAC3 Latched
DAC4 Transparent
DAC4 Latched
No Operation
A0, A1
LD
Figure 2. Input Control Logic (Simplified)
Block Diagram
Table 1. Truth Table
D7
MSB
0
0
D6
D5
D4
D3
D2
D1
D0 DAC Output Voltage
D
LSB V
Oi
= V
REFN
+ (V
Ri –
AGND) (
256
)
0
1
V
REFN
1
(V
Ri
– V
REFN
) ( 256 ) + V
REFN
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
254
(V
Ri
– V
REFN
) ( 256 ) + V
REFN
255
(V
Ri
– V
REFN
) ( 256 ) + V
REFN
Note: These outputs must be ratioed up for gain in the output amplifier.
Table 2. DAC Transfer Function
Analog Output vs. Digital Code (With V
REF
Shorted to INV)
Rev. 1.00
6