MP7641
ELECTRICAL CHARACTERISTICS TABLE
Description
DIGITAL TIMING
SPECIFICATIONS
2, 4
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Reset Pulse Width
Clock Edge to Load Rising Edge
Clock Edge to Load Falling Edge
Load Falling Edge to SDO
3-state Enable
Load Rising Edge to SDO
3-state Disable
Load Falling Edge to CLK Disable
Load Rising Edge to CLK Enable
LD Set-up Time with Respect
to CLK
t
CH
, t
CL
t
DS
t
DH
t
PD
t
LD
t
RST
t
CKLD1
t
CKLD2
t
HZ1
t
HZ2
t
LDCK1
t
LDCK2
t
LDSU
40
10
15
40
100
50
100
0
50
35
25
35
15
100
60
100
0
60
50
40
50
20
50
10
15
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Min
25
°
C
Typ
Max
Tmin to Tmax
Min
Max
Units
Conditions
NOTES
Full Scale Range (FSR) is 3V.
2
Guaranteed but not production tested.
3
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
4
See Figures 2 and 3.
5
For reference input pulse: t
R
= t
F
> 100 ns.
1
Specifications are subject to change without notice
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
