MP7636A
TIMING DIAGRAM
t
CS
t
V
V
CH
IH
50%
50%
CS, BYTE1/BYTE2
IL
t
W
V
IH
50%
50%
WR
V
V
IL
t
DS
t
DH
IH
50%
50%
DATA BITS
V
IL
t
S
I
I
OUT1, OUT2
SETTLED TO
+0.01%
IOUT2
:
DAC Current Output 2 Bus.
IOUT2 is a complement of IOUT1. The ladder termina-
tion has been tied to IOUT2 internally.
DEFINITION OF CONTROL SIGNALS:
CS:
Chip Select (Active low).
It will enable WR1.
RFB
:
Feedback Resistor.
WR1: Write 1 (Active low)
This internal feedback resistor should always be used
(not an external resistor) since it matches the resistors
in the DAC and tracks these resistor overtemperature.
The WR1 is used to load the digital data bits (DB) into
the input latch.
BYTE1/BYTE2: Byte sequence control.
The BYTE1/BYTE2 control pin is used to select MSB
and LSB both input latches.
VREF
:
Reference Voltage Input.
This input connects an external precision voltage
source to the internal DAC. The VREF can be selected
over the range of +25V to –25V or the analog signal for
a 4-quadrant multiplying mode application.
WR2: Write 2 (Active low).
It will enable XFER.
VDD
:
Power Supply Voltage.
XFER: Transfer control signal (Active low).
This signal, in combination with WR2, causes the
16-bit data which is available in the input latches to
transfer to the DAC register.
This is the power supply pin for the part. The VDD can
be from +5 V DC to +15 V DC, however optimum volt-
age is +15 V DC.
AGND: Analog Ground.
Back gate of the DAC N-channel current steering
DB0 to DB15: Digital Inputs.
DB0 is the least significant digital input (LSB) and
DB15 is the most significant digital input (MSB).
switches.
DGND: Digital Ground .
IOUT1
:
DAC Current Output 1 Bus.
The timing diagrams for updating the DAC register are shown
in Figures 1 and 2.
IOUT1 is a maximum for a digital code of all 1’s in the
DAC register, and is zero for all 0’s in the DAC register.
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
