MP7612
ELECTRICAL CHARACTERISTICS (CONT’D)
25°C
Typ
Tmin to Tmax
Min Max
Parameter
Symbol
Min
Max
Units
Test Conditions/Comments
3
DIGITAL INPUTS
Logic High
Logic Low
Input Current
V
V
2.4
V
V
µA
pF
IH
0.8
+10
8
IL
I
L
1
Input Capacitance
C
L
ANALOG OUTPUTS
Output Swing
–V +1.4
EE
V
CC
–1.4
V
Output Drive Current
Output Impedance
Output Short Circuit Current
–5
5
mA
Ω
mA
mA
mA
mA
R
1
O
I
25
30
40
55
+FS to AGND
SC
+FS to V
EE
–FS to AGND
–FS to V
CC
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
V
V
4.5
0.5
V
V
OH
OL
POWER SUPPLIES
5
V
V
Voltage
Voltage
V
V
+1.5 12 12.75
V +1.5 12.75
REF
V
V
V
CC
CC
REF
5
V
–12.75
4.5
–12
5
8
–5
5.5
10
–12.75
4.5
–5
5.5
EE
EE
DD
CC
DV Voltage
DV
I
DD
Positive Supply Current
Negative Supply Current
Digital Supply Current
Power Dissipation
10 mA
20 mA
2
Bipolar zero
Bipolar zero
Bipolar zero
Bipolar zero
I
15
20
EE
DD
ISS
I
2
mA
PD
320
420
450 mW
ANALOG GROUND CURRENT
1
Per Channel
I
±60
µA
See Application Notes
AGND
DIGITAL TIMING
SPECIFICATIONS
1,4
V = 0, V = 5.0, C = 20 pF
IL IH L
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
t
, t
35
15
15
ns
ns
ns
ns
ns
ns
ns
CH CL
t
t
DS
DH
t
40
PD
t
35
50
140
0
LD
PR
t
Clock Edge to Load Time
t
t
Note: t and t
cannot both
CKLD1
CKLD2
LD
CKLD2
be min. since t
=t
+t
CKLD1 CKLD2 LD
LD Falling Edge to SDO
Tri-state Enable
LD Rising Edge to SDO
Tri-state Disable
t
50
ns
ns
HZ1
t
50
HZ2
LD Rising Edge to CLK Enable
LD Set-up Time with Respect
to CLK
t
t
50
30
ns
ns
LDCK
LDSU
Rev. 3.00
5
EXAR [ EXAR CORPORATION ]
