MP7612
ELECTRICAL CHARACTERISTICS (CONT’D)
25
°
C
Typ
Tmin to Tmax
Min
Max
Parameter
DIGITAL INPUTS
3
Logic High
Logic Low
Input Current
Input Capacitance
1
ANALOG OUTPUTS
Output Swing
Output Drive Current
Output Impedance
Output Short Circuit Current
–V
EE
+1.4
–5
R
O
I
SC
V
CC
–1.4
5
1
25
30
40
55
V
mA
Ω
mA
mA
mA
mA
V
IH
V
IL
I
L
C
L
2.4
0.8
+10
8
V
V
µA
pF
Symbol
Min
Max
Units
Test Conditions/Comments
+FS to AGND
+FS to V
EE
–FS to AGND
–FS to V
CC
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
POWER SUPPLIES
V
CC
Voltage
5
V
EE
Voltage
5
DV
DD
Voltage
Positive Supply Current
Negative Supply Current
Digital Supply Current
Power Dissipation
ANALOG GROUND CURRENT
Per Channel
1
DIGITAL TIMING
SPECIFICATIONS
1,4
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
LD Falling Edge to SDO
Tri-state Enable
LD Rising Edge to SDO
Tri-state Disable
LD Rising Edge to CLK Enable
LD Set-up Time with Respect
to CLK
t
CH
, t
CL
t
DS
t
DH
t
PD
t
LD
t
PR
t
CKLD1
t
CKLD2
t
HZ1
t
HZ2
t
LDCK
t
LDSU
35
15
15
40
35
50
140
0
50
50
50
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
AGND
±60
µA
See Application Notes
V
CC
V
EE
DV
DD
I
CC
I
EE
I
DD
PD
ISS
V
REF
+1.5 12
–12.75
–12
4.5
5
8
15
320
12.75
–5
5.5
10
20
2
420
V
REF
+1.5 12.75
–12.75
–5
4.5
5.5
10
20
2
450
V
V
V
mA
mA
mA
mW
V
OH
V
OL
4.5
0.5
V
V
Bipolar zero
Bipolar zero
Bipolar zero
Bipolar zero
V
IL
= 0, V
IH
= 5.0, C
L
= 20 pF
Note: t
LD
and t
CKLD2
cannot both
be min. since t
CKLD1
=t
CKLD2
+t
LD
Rev. 3.00
5