MP7611
Data
Input/Output
Bus
Address
A0-A2
Chip Select
CS
Load Latch A
LD1
Load Latch B
LD2
1
0
1
0
1
0
1
0
1
0
+FS
--FS
t
SD
don’t care
t
CS1
t
LD1W
t
LD1LD2
t
LD2W
t
AS
t
AH
t
CH1
don’t care
t
DS
t
DH
Analog Output
Figure 1. Loading Latch A and Updating Latch B
Notes:
(1) Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable
in the above diagram.
(2) R1 = R2 = 1.
(3) For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).
Address
A0-A2
Chip Select
CS
Data Readback
RD
Digital Output Data
D0 to D113
1
0
1
0
1
0
1
0
don’t care
t
AS
t
AH
don’t care
t
CS2
t
DA
t
RD
t
CH2
t
DR
HIGH-Z
HIGH-Z
Figure 2. Read Back First Latch Bank of One DAC
Notes:
(1) Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable
in the above diagram.
(2) R1 = R2 = 1.
R1
R2
t
R1W
1
0 Reset first latch bank to
1000 . . . . .0000
1
0 Reset second latch bank to 1000 . . . . .0000 and analog
output to zero volt.
t
R2W
Figure 3. Reset Operations
Rev. 3.01
7
EXAR [ EXAR CORPORATION ]
