MP7610
The MP7610 is equipped with a serial data (3-wire standard)
µ-processor logic interface to reduce pin count, package size,
and board wire (space). If the LD signal is high, the CLK signal
loads the digital input bits (SDI) into the shift register (4 bits ad-
dress A3 to A0 plus 14 bits data D13 to D0 for the MP7610). The
LD signal going low loads the data into the selected DAC. The
LD signal going low also disables the serial data (SDI), output
(SDO tri-stated) and the CLK input. This design tremendously
reduces digital noise and glitch transients into the DACs due to
free running CLK and SDI. Note also that the preset signal
(RST) resets all analog outputs to 0 volt regardless of digital in-
puts.
Function
A3 A2 A1 A0
LD
CLK
RST
SDI
SDO
0→1
Shift Data In
and Out
X
X
X
X
X
X
X
X
1
Data Input
Valid
Data Output
Valid
1
1
Repeat
Stop Shifting
Data In and
Out
0
X
X
Hi-Z
Load DACs
0
0
0
0
No Operation
1→0
1→0
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1→0
1→0
1→0
1→0
1→0
1→0
No Operation
No Operation
No Operation
X
X
Hi-Z
Hi-Z
1
1
1
1
1
1
0
1
1
1
Reset all DACs
to 0 V
X
X
X
X
X
X
0
X
X
Table 1. Digital Function Truth Table
Serial In/Serial Out
Note: For timing information See Electrical Characteristics.
2•D
)
Output Voltage = 2 • Vr (--1 +
Hex Code
Binary Code
(Vr = +5 V)
10 • (--1 + 0) = --10
16384
O O O O
00000000000000
16382
16384
10 • (--1 +
) = --1.22 mV
1 F F F
2 O O O
2 O O 1
01111111111111
10000000000000
10000000000001
16384
10 • (--1 +
) = 0
16384
16386
10 • (--1 +
) = 1.22 mV
16384
32766
16384
10 • (--1 +
) = 9.99878
3 F F F
11111111111111
Table 2. MP7610 Ideal DAC Output vs . Input Code
Note: See Electrical Characteristics for real system accuracy
Rev. 4.01
8
EXAR [ EXAR CORPORATION ]
