MP7543
TIMING DIAGRAM
t
SRI
SR1
t
DS1
, t
DS2
, t
DS4
Strobe Input
(STB1, STB2, STB4
(Note)
1
t
STB1
t
STB2
t
STB4
LOADING REGISTER A
t
ASB
LD1 AND LD2
Note:
Strobe Waveform is Inverted if
STB3 is Used to Strobe Serial Data Bits
into Register A
Loading Register B
with Contents of Register A
t
LD1
t
LD2
Bit 1
MSB
Bit 2
t
DH1
, t
DH2
, t
DH4
2
11
12
Bit 11
Bit 12
LSB
MP7543 Logic Inputs
Register A Control Inputs
STB4
0
0
0
1
1
X
X
X
X
0
X
X
STB3
1
1
0
0
X
X
1
X
STB2
0
0
0
0
X
X
X
1
0
1
1
1
X
1
X
0
X
X
1
0
Clear Register B to code 0000 0000 0000 (Asynchronous)
No Operation (Register B)
Load Register B with the contents of Register A
1, 3
3
3
No Operation (Register A)
3
STB1
Register B Control Inputs
CLR
X
X
X
X
LD2
X
X
X
X
LD1
X
X
X
X
Data appearing at SRI strobed into Register A
Data appearing at SRI strobed into Register A
Data appearing at SRI strobed into Register A
Data appearing at SRI strobed into Register A
2, 3
2, 3
2, 3
2, 3
MP7543 Operation
Notes
NOTES
1. CLR = 0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A.
2. Serial data is loaded into Register A MSB first, on edges shown
is positive edge,
is negative edge.
3. 0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.
Table 1. Truth Table
Rev. 2.00
6