MP7533
ORDERING INFORMATION
Package
Type
Temperature
INL
(LSB)
DNL
(LSB)
Gain Error
(% FSR)
Part No.
Range
–40 to +85°C
–40 to +85°C
–40 to +85°C
–40 to +85°C
–40 to +85°C
Plastic Dip
Plastic Dip
Plastic Dip
SOIC
MP7533JN
MP7533KN
MP7533LN
MP7533JS
MP7533KS
+2
+1
+1
+1
+1
+1
+1
1.5
1.5
1.5
1.5
1.5
+1/2
+2
SOIC
+1
–40 to +85°C
–40 to +85°C
SOIC
MP7533LS
MP7533AD
+1/2
+2
+1
+1
1.5
1.5
Ceramic Dip
–40 to +85°C
–40 to +85°C
–55 to +125°C
Ceramic Dip
Ceramic Dip
Ceramic Dip
MP7533BD
MP7533CD
MP7533SD*
+1
+1/2
+2
+1
+1
+1
1.5
1.5
1.5
–55 to +125°C
–55 to +125°C
Ceramic Dip
Ceramic Dip
MP7533TD*
MP7533UD*
+1
+1
+1
1.5
1.5
+1/2
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
1
16
I
1
2
3
4
5
6
7
8
16
R
OUT1
FB
2
15
14
13
I
15
14
13
12
11
10
9
V
V
OUT2
REF
3
4
GND
(MSB) BIT 1
BIT 2
DD
See
Pin Out
at Left
BIT 10 (LSB)
BIT 9
BIT 8
BIT 7
BIT 6
5
6
7
8
12
11
10
9
BIT 3
BIT 4
BIT 5
16 Pin CDIP, PDIP (0.300”)
D16, N16
16 Pin SOIC (Jedec, 0.300”)
S16
PIN OUT DEFINITIONS
PIN NO.
NAME
DESCRIPTION
Current Output 1
PIN NO.
NAME
BIT 6
DESCRIPTION
1
2
3
4
5
6
7
8
I
I
9
Data Input Bit 6
OUT1
Current Output 2
Ground
10
11
12
13
14
15
16
BIT 7
BIT 8
BIT 9
BIT 10
Data Input Bit 7
OUT2
GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
Data Input Bit 8
Data Input Bit 1 (MSB)
Data Input Bit 2
Data Input Bit 3
Data Input Bit 4
Data Input Bit 5
Data Input Bit 9
Data Input Bit 10 (LSB)
Positive Power Supply
Reference Input Voltage
Internal Feedback Resistor
V
V
DD
REF
R
FB
Rev. 2.00
2