MP7528
Write Mode: When CS and WR are both low the selected
DAC is in the write mode. The input data latches of the selected
DAC are transparent and its analog output responds to activity
on DB0-DB7.
INTERFACE LOGIC INFORMATION
DAC Selection: Both DAC latches share a common 8-bit in-
put port. The control input DACA/DACB selects which DAC can
accept data from the input port.
Hold Mode: The selected DAC latch retains the data which
was present on DB0-DB7 just prior to CS and WR assuming a
high state. Both analog outputs remain at the values corre-
sponding to the data in their respective latches.
Mode Selection: Inputs CS and WR control the operating
mode of the selected DAC. See Mode Selection Table below:
DAC A/DAC B
CS
WR
DAC A
DAC B
L
L
L
H
X
L
L
X
H
Write
Hold
Hold
Hold
Hold
Write
Hold
Hold
H
X
X
L = LOW state, H = HIGH state, X = Don’t care state
Table 1. Mode Selection Table
t
CH
V
DD
t
CS
CS
0
t
AH
V
V
DD
t
AS
DAC A/DAC B
0
DD
t
WR
WR
0
DD
0
t
t
DH
DS
V
V
V
V
IH
V
IL
IH
DATA IN
(DB0-DB7)
DATA IN
STABLE
IL
NOTES:
1. All input signal rise and fall times measured from 10% to 90% of V
.
DD
V
V
= +5 V, t = t = 20 ns
DD
DD
r f
= +15 V, t = t = 40 ns
r
f
2. Timing measurement reference level is V + V / 2
IH
IL
Figure 1. Write Cycle Timing Diagram
Rev. 2.00
8
EXAR [ EXAR CORPORATION ]
