MP7228
Decoding two bits to three, a 1% change in any one of the
converter’s three decoded current sources affects the output by
no more than 0.25% of full scale, compared with 0.5% in a con-
ventional R-2R type CMOS DAC.
D/A CONVERTER SECTION
The MP7228 contains eight matched, 8-bit, voltage-mode
digital-to-analog converters (DACs) which incorporate an MPS
pioneered unique bit decoding technique. This decoding
scheme reduces the maximum binary weight carried by any re-
sistor switch, reducing the accuracy required of the switches
and resistor network.
The output voltages have the same polarity as the reference
voltage, allowing single supply operation. The voltage refer-
ence range is from +2V to +10V. Each DAC uses a highly-stable,
thin-film, ladder network and high-speed NMOS switches.
Figure 1. shows a simplified circuit diagram for one channel.
In the MP7228, the first three MSBs are decoded into three
equal current sources, each contributing 25% of the full scale
output current.
–
V
OUT
2R
2R
2R
+
4R
4R
4R
4R
4R
4R
V
REF
GND
2 to 3 Decoder
Switch Drivers
Shown for all 1s on DAC
Figure 1. Simplified D/A Circuit Diagram
Output Buffer Amp
V
REF
Input
Each D/A converter output is buffered by a unity gain nonin-
verting BiCMOS amplifier which has slew rate greater than 4 V/
µs. The output buffer settles to ꢀ1/2 LSB in less than 4µs when
drivingaloadof2kΩ inparallelwith100pFwithafullscaletransi-
tion from 0V to +10V or from +10V to 0V . The buffers can drive
2kΩ and 500pF to 10V levels without oscillation.
The VREF and GND are common to all eight DACs and set the
full-scale output. The input impedance of the VREF pin is the par-
allel combination of the eight individual DAC reference imped-
ances and is code dependent. This impedance varies from 2kΩ
to 500kΩ. Therefore, it is very important that the external refer-
ence source output impedance is low enough so that its output
voltage will not be affected by the varying digital code. Due to
transient currents at the VREF input during digital code changes,
a 0.1µF or greater decoupling capacitor on that VREF input is
recommended. The input capacitance at the VREF pin is also
code dependent and typically varies from less than 120pF to
less than 350pF.
A simplified circuit diagram of the output buffer is shown in
Figure 2. The Input stage is provided by BiCMOS PNP transis-
tors with resulting lower input offset voltage, offset voltage drift
over time and noise when compared to MOS process . The am-
plifier output stage uses a substrate NPN bipolar device to pro-
vide a low output impedance, high-output current capability.
Each VOUT voltage can be represented by a digitally pro-
grammable voltage source using the following expression :
The MP7228 is specified for single or dual power supply op-
eration, with only the buffer amplifier outputs using VSS supply
current . Operating the MP7228 from dual supplies will improve
the negative going output settling time near ground. In dual sup-
ply voltage operation, the output amplifier can sink 500µA when
VOUT = 0 V.
VOUT = Dn X VREF/256
where Dn is the decimal equivalent to the digital input code
and can vary from 0 to 255.
Rev. 2.00
7
EXAR [ EXAR CORPORATION ]
