MP7226
VDD
To DAC1 Latch Enable
To DAC2 Latch Enable
To DAC3 Latch Enable
To DAC4 Latch Enable
A0
A1
1 of 4
Decoder
VIN
Output
VSS
WR
AGND
Figure 3. Input Control Logic
Figure 2. Simplified Output Buffer Amplifiers
The amplifiers outputs may be shorted to ground. However,
the power dissipation of the package should not exceed the
maximum limit.
WR
H
A1
X
A0
X
Operation
No Operation;
Device Not Selected
DAC 1 Transparent
L
L
L
Digital Inputs
DAC 1 Latched
L
L
L
H
L
DAC 2 Transparent
DAC 3 Transparent
DAC 4 Transparent
L
L
L
All of the digital inputs to this DAC maintain TTL level inter-
face compatibility and can also be driven directly with 5V CMOS
logic inputs. The digital inputs are ESD protected to a rating of
2000 volts.
H
H
H
Table 1. Truth Table
Digital Interface Logic
The MP7226 allows direct interface to most microprocessor
buses without additional interface circuitry.
t
AS
t
AH
Figure 3. shows the input control logic circuit diagram and
Table 1. shows the control logic truth table and operation for
WR, A1, A0. The address lines A0, and A1 determine which
DAC will accept the input data. The WR input determines
whether the selected DAC is transparent (output follows the in-
put), latched, or no operation. The WR input will also inhibit
poweronresetoftheDAClatchesto0, ifitsinitialstate=0after5
µs of power.
5 V
0 V
Address
t
WR
WR
5 V
0 V
t
t
DH
DS
5 V
0 V
V
V
INH
INL
Data
Figure 4. showsthewritecycletimingdiagram. WhentheWR
signal is low, the input latch of the selected DAC is transparent,
and the DAC’s output corresponds to the value present on the
data bus. On some data buses, data is not always valid for the
entire period that the WR signal is low and can cause unwanted
data at the output. Ensuring that the write pulse (WR) conforms
to the data hold time, (t4) spec will prevent this problem.
NOTE: When the WR signal is low, the input latch of the se-
lected DAC is transparent and any invalid data at this time will
cause erroneous output.
Figure 4. Write Cycle Timing Diagram
Rev. 2.00
8
EXAR [ EXAR CORPORATION ]
