CLC2011, CLC4011
In order to determine P , the power dissipated in the load
needs to be subtracted from the total power delivered by the
supplies.
D
2.5
2
TSSOP-14
P = P
- P
load
D
supply
SOIC-14
1.5
1
Supply power is calculated by the standard power equation.
SOIC-8
P
supply
= V
× I
supply RMSsupply
V
= V - V
S+ S-
supply
0.5
0
MSOP-8
-20
Power delivered to a purely resistive load is:
-40
0
20
40
60
80
100
120
2
Ambient Temperature (°C)
P
load
= ((V
)
)/Rload
eff
load RMS
Figure 5. Maximum Power Derating
The effective load resistor (Rload ) will need to include
eff
the effect of the feedback network. For instance, Rload in
Figure 3 would be calculated as:
eff
Input Common Mode Voltage
The common mode input range extends to 250mV below
ground and to 250mV above Vs, in single supply operation.
Exceeding these values will not cause phase reversal.
However, if the input voltage exceeds the rails by more
than 0.5V, the input ESD devices will begin to conduct. The
output will stay at the rail during this overdrive condition. If
the absolute maximum input voltage (700mV beyond either
rail) is exceeded, externally limit the input current to 5mA
as shown in Figure 6.
R || (R + R )
L
f
g
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, P can be found from
D
P = P
D
+ P
- P
Quiescent
Dynamic load
10k
Input
+
-
Output
Quiescent power can be derived from the specified I values
S
along with known supply voltage, V
. Load power can
supply
be calculated as above with the desired signal amplitudes
using:
Figure 6. Circuit for Input Current Protection
(V
)
= V
/ √2
peak
load RMS
( I
)
= ( V
)
/ Rload
eff
load RMS
load RMS
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
possible unstable behavior. Use a series resistance, R ,
S
P
= (V - V
)
× ( I )
load RMS
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 7.
Dynamic
S+
load RMS
Assuming the load is referenced in the middle of the power
rails or V /2.
Input
+
-
supply
Rs
Output
CL
RL
Rf
The CLC2011 is short circuit protected. However, this may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded under all conditions. Figure 5
shows the maximum safe power dissipation in the package
vs. the ambient temperature for the packages available.
Rg
Figure 7. Addition of R for Driving Capacitive Loads
S
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exar.com/CLC2011
Rev 1D
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