Data Sheet
Power Dissipation
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
Power dissipation should not be a factor when operating
under the stated 2kΩ load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature
is not exceeded. Guidelines listed below can be used to
verify that the particular application will not cause the
device to operate beyond it’s intended operating range.
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
Assuming the load is referenced in the middle of the
power rails or V /2.
supply
The CLC1009 is short circuit protected. However, this may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded under all conditions. Figure 5
shows the maximum safe power dissipation in the package
vs. the ambient temperature for the packages available.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value
2
Theta (Ө ) is used along with the total die power
JA
JA
SOIC-8
dissipation.
MSOP-8
1.5
T
= T + (Ө × P )
Ambient JA D
Junction
Where T
is the temperature of the working environment.
Ambient
1
In order to determine P , the power dissipated in the load
D
needs to be subtracted from the total power delivered by
the supplies.
0.5
SOT23-6
P = P
- P
load
SOT23-5
D
supply
0
Supply power is calculated by the standard power
equation.
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
P
= V
× I
supply
supply RMS supply
Figure 5. Maximum Power Derating
V
= V - V
S+ S-
supply
Power delivered to a purely resistive load is:
Driving Capacitive Loads
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
Increased phase delay at the output due to capacitive
loading can cause ringing, peaking in the frequency
response, and possible unstable behavior. Use a series
The effective load resistor (Rload ) will need to include
the effect of the feedback network. For instance,
eff
resistance, R , between the amplifier and the load to
Rload in Figure 3 would be calculated as:
S
eff
help improve stability and settling performance. Refer to
Figure 6.
R || (R + R )
L
f
g
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Input
+
-
Rs
Output
Here, P can be found from
D
CL
RL
Rf
P = P
+ P
- P
D
Quiescent
Dynamic Load
Rg
Quiescent power can be derived from the specified I
S
values along with known supply voltage, V
power can be calculated as above with the desired signal
amplitudes using:
. Load
Supply
Figure 6. Addition of R for Driving Capacitive Loads
S
(V
)
= V
/ √2
LOAD RMS
PEAK
( I
)
= ( V
)
/ Rload
eff
LOAD RMS
LOAD RMS
©2009-2013 Exar Corporation
10/15
Rev 1D
EXAR [ EXAR CORPORATION ]
