CLC1003
R = R ||R
f
The complete equation can be simplified to:
t
g
This equation can be rearranged to solve for R :
2
2
)
g
2
o
v
= 3 ∗ 4kT ∗ G ∗RT + e G + 2 ∗ i ∗RT
(
)
(
)
(
n n
R = (R * R ) / (R - R )
g
t
f
f
t
The other consideration is desired gain (G) which is:
G = (1 + R /R )
It’s easy to see that the effect of amplifier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
f
g
By plugging in the value for R we get
g
large R values at lower gains.
t
R = G * R
f
t
And R can be written in terms of R and G as follows:
g
t
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
R = (G * R ) / (G - 1)
g
t
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
2
)
2
ꢀ■
Include 6.8µF and 0.1µF ceramic capacitors for power supply
VI
=
V
+ I ∗ RT
(
(
)
OS
IO
OS
decoupling
ꢀ■
Place the 6.8µF capacitor within 0.75 inches of the power pin
And the output offset is:
ꢀ■
Place the 0.1µF capacitor within 0.1 inches of the power pin
2
)
2
)
ꢀ■
Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
VO
= G ∗
V
+ I ∗ RT
(
(
OS
IO
OS
ꢀ■
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
R
R
f
g
Evaluation Board Information
+ –
+ –
The following evaluation boards are available to aid in the
testing and layout of these devices:
–
R
CLC1003
+
g
+ –
+ –
Evaluation Board #
CEB002
Products
+
–
R
L
CLC1003 in TSOT
CLC1003 in SOIC
CEB003
Figure 7: Complete Equivalent Noise Circuit
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 8-12 These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
The complete noise equation is given by:
2
)
2
2
2
2
RF
RF
v
=
v
+
e
1 +
+ i ∗ RT 1 +
+ i ∗ RF
(
o
orext
n
bp
bn
RG
RG
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
Where V
is given by:
is the noise due to the external resistors and
orext
2
2
2
F
2
RF
RF
= e 1 +
+ e ∗
+ e
v
o
n
G
RG
RG
© 2007-2014 Exar Corporation
14 / 17
exar.com/CLC1003
Rev 1D
EXAR [ EXAR CORPORATION ]
