2.2 Clock Domains
The 820x logic operates with six main clock domains:
• PCIe Serdes, PCIe Core, DMA, Probe, Pad engine and JTAG (125MHz from PCIe
Serdes PLL)
• Hash Engine (278MHz from CLK_RST_Gen)
• LZS Engine interface logic and Encrypt Engine (208MHz from CLK_RST_Gen)
• LZS Engine Core Logic (417MHz from CLK_RST_Gen)
• GZIP Engine (250MHz from CLK_RST_Gen)
• PK Core (375MHz from CLK_RST_Gen)
2.3 Clock Gating
Hifn’s 820x supports aggressive static and dynamic clock gating.
Static clock gating will disable the clock to the Channel Managers, Data Process Channels,
PKP Manager, PKP Engine, and RNG if the corresponding register enable bits are set to
zero. If the software disables a Channel Manager, the clock to all modules in this channel
will also be disabled.
Dynamic clock gating will disable the clock for all unused engines in Data Process Channels
for each command. For example, if one command only compresses data, the clock of the
Pad Engine, Hash Engine and Encrypt Engine will be gated automatically.
The shaded regions in Figure 2-8 show which 820x blocks employ clock gating.
820x – Data Sheet, DS-0157-D
Page35
Hifn Confidential
EXAR [ EXAR CORPORATION ]
