Figure 5-11. Encryption Engine Block Diagram
5.10.1
Encryption In_AFIFO & Out_AFIFO
The Encryption In_AFIFO and Out_AFIFO are used to transfer data and control signals
between the DMA clock domain (125M) and the Encryption Engine interface controller clock
domain (200M).
Both the In_AFIFO and Out_AFIFO are implemented as 39 x 16 bit flip-flops.
5.10.2
Encryption Interface Controller
The Encryption Interface Controller (EIC) is the communication bridge between the
In_AFIFO, Out_AFIFO, AES core, and 3DES core. The main functions of the EIC are:
• Read the source data from the In_AIFIO, pass through the header and tail of data
stream to the next engine (Out_AFIFO), and send the remaining data to the AES
core/3DES core according to the ENC_Head_Count and ENC_Source_Count.
• Control the operation flow of the AES and 3DES cores.
• Read the result data from the AES Core/3DES cores, merge the tail of the source
data stream and the result data into a double word, and send it to the Out_AFIFO.
• Report the AES and 3DES core status to the Channel Manager after each command
completes.
5.10.3
Encryption AES and 3DES Cores
The AES and 3DES cores are Hifn IP. The Encryption/Decryption engine supports AES-GCM,
CBC, CTR and ECB with 128, 192 or 256 bit keys, AES-XTS with 256 or 512 bit keys, and
3DES.
820x – Data Sheet, DS-0157-D
Page125
Hifn Confidential
EXAR [ EXAR CORPORATION ]
