3.3 Command Operation Sequence
The 820x has a high performance DMA engine that supports two command pointer rings
using a round-robin arbitration scheme. Figure 3-25 shows how the 820x and the host
software work together to process a command. The flow is described in the figure below.
Figure 3-25. Command Process Flow Example
1. Host configures the 820x control registers (Refer to Chapter 6 for details).
2. Host sets up Command Pointer Ring 0 and Command Pointer Ring 1 and writes
the command structures into host memory.
3. Host writes the source data into the source buffers.
4. Host writes the index number of the commands into the Command Pointer Ring
using the 820x Command Pointer Ring Write Pointer (Wcp) register and updates
its own Command Pointer Ring Write Pointer (Wch). The 820x maintains a
Command Pointer Ring Read Pointer (Rcp) register which may be read by the
host at any time. It is the responsibility of the host not to overflow the Command
Pointer Ring by ensuring that the write pointer never advances to meet the read
pointer. If several commands are ready for submission at the same time, the host
may build the command structures for all these commands and then issue a
single write to the write pointer register to improve efficiency.
820x – Data Sheet, DS-0157-D
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