• Push the source descriptor head and tail pointers into the pointer FIFO in the
Channel Manager Inbound Data Controller (IDC) when sending source data read
requests (The head and tail pointers indicate the valid bytes in a single quad-word
as the source buffer starting address and length is arbitrary)
5.1.5
Write Request Controller
The Write Request controller (WRC) arbitrates the write requests from multiple sources,
builds the TLP, and sends write requests to the POM. The main functions of the WRC are:
• Store the destination descriptor starting address and byte count
• Arbitrate destination write requests from both channel managers and the PKP
manager
• Split the destination descriptor into TLP write requests and send those requests to
the POM
• Generate a Free Pool write request if a Free Pool entry is used by the channel
manager
• Generate the command structure result field and result ring write requests when a
command completes
• Update the result ring write pointer after a command completes
5.1.6
Completion Controller
The Completion Controller (CC) distributes completion data to the proper destination
according to the PCIe tags, which tag a completion. The main functions of the Completion
Controller are:
• Decode the command structure and send the command to a channel manager
• Write the source descriptors to the RRC source descriptor buffer and destination
descriptors to the WRC destination descriptor buffer
• Write the completion data to the corresponding channel manager's source buffer
• Maintain the read request record table
5.2 Configuration Registers
The Configuration Registers (CFG_REGS) module implements all 820x registers accessed by
the host through the PCIe bus. The main functions of the Configuration Registers are:
• Implement all registers
• Respond to PCIe memory write and read request from the PIM
• Provide global configuration signals to all other modules
820x – Data Sheet, DS-0157-D
Page109
Hifn Confidential
EXAR [ EXAR CORPORATION ]
