6.5.4
RNG Interrupt Control/Status Register
The RNG Interrupt Control/Status register allows the host software to read the 820x RNG
interrupt status. The error bits in this registers will be set if that error event has occurred.
If the error's corresponding enable bit is set in the RNG Interrupt Enable Register, an
interrupt will be generated to the host.
The LEG2_XOR_ERR, LEG1_XOR_ERR and TREE_XOR_ERR pertain to internal RNG logic. If
any of these errors occur, please contact Hifn customer support.
Type:
Offset
Read/Write one to clear
x‘080C’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Bits
Reset
Reserved
31:6
0
Reserved.
RING_FAIL_FLAG
Ring Failure Flag.
One or more ring oscillators failed to oscillate.
5
4
3
2
0
0
0
0
0
1
Ring failure not detected
Ring failure detected
LEG2_XOR_ERR_FLAG
LEG1_XOR_ERR_FLAG
TREE_XOR_ERR_FLAG
Leg 2 XOR Error Flag.
An error was detected in the RNG Leg 2 XOR logic.
0
1
Leg 2 XOR error not detected
Leg 2 XOR error detected
Leg 1 XOR Error Flag.
An error was detected in the RNG LEG 1 XOR logic.
0
1
Leg 1 XOR error not detected
Leg 1 XOR error detected
Tree XOR Error Interrupt Flag.
An error was detected in the RNG Tree XOR logic.
0
1
Tree XOR error not detected
Tree XOR error detected
820x – Data Sheet, DS-0157-D
Page174
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EXAR [ EXAR CORPORATION ]
