6.4 Public Key Processor Control Registers
The Public Key Processor (PKP) implements a group of registers, through which the host
may control the PKP engine and execute complex computations. The PKP Manager fetches
source data and instructions from host memory, and then sends the computation result to
host memory according to the PKP command registers.
To increase performance, the 820x implements two pairs of PK cores; a pair consists of one
master PK core and one slave PK core.
6.4.1
Public Key Enable Register
The Public Key Engine register is used to enable/disable either of the Public Key Engine
pairs and the Public Key Engine.
Type:
Offset
Read/Write
x‘0580’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Description
Bits
Reset
31:3
0
Reserved.
DIS_PK_PAIR1
Disable Public Key Pair 1
If the PK core 1 is disabled, the PK core 1 clock is
also disabled to save power.
2
1
0
0
0
1
Enable Public Key Pair 1
Disable Public Key Pair 1
DIS_PK_PAIR0
Disable Public Key Pair 0
If the PK core 0 is disabled, the PK core 0 clock is
disabled to save power.
0
1
Enable Public Key Pair 0
Disable Public Key Pair 0
PK_EN
Public Key Enable
Note: the host software should first enable the PKP,
and then write commands to the PKP command
entry.
0
0
0
Disable the PKP Manager and PKP Engine and
clock
1
Enable the PKP Manager and PKP Engine
820x – Data Sheet, DS-0157-D
Page158
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