6.2.15
Channel Manager 0-1 Error Status Register
If a 820x Channel Manager detects an error, the 820x will set the appropriate bit in this
register. The Host may read the Channel Manager Error Status register to determine the
source of the error. This information may also be read from the entry in the result ring.
Because the Channel Managers continue to process commands after an error, the error bits
in this register may be overwritten. It is recommended that the host validates the error bit
with the result ring error from the command.
Type:
Offset
Read/Write to clear
x‘0260’
Channel Manager 0 error status
Channel Manager 1 error status
x‘0264’
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Description
Channel Manager Data CRC error
Bits
Reset
CM_DCRC
31
0
0
1
Channel Manager did not detect data CRC error
Channel Manager detected data CRC error
CM_KCRC
CM_ECC
Channel Manager Key CRC error
30
29
0
0
0
1
Channel Manager did not detect key CRC error
Channel Manager detected key CRC error
Channel Manager ECC/Parity error
0
Channel Manager did not detect ECC/Parity
error on this channel
1
Channel Manager detected ECC/Parity error
on this channel
Reserved
PAD_ERR
28
27
0
0
Reserved
Pad Engine Padding Error
0
1
Pad Engine did not detect padding error
Pad Engine detected padding error
820x – Data Sheet, DS-0157-D
Page151
Hifn Confidential
EXAR [ EXAR CORPORATION ]
