6.5.3
RNG Interrupt Enable Register
The RNG Interrupt Enable register allows the host software to enable/disable the 820x RNG
interrupts. If a RNG Enable bit is set to one, the interrupt is enabled for that event. If the
enable bit is cleared to zero, the interrupt will be disabled and will not interrupt the host,
but the interrupt will appear in the RNG Interrupt Control / Status register as expected.
The LEG2_XOR_ERR, LEG1_XOR_ERR and TREE_XOR_ERR pertain to internal RNG logic. If
any of these errors occur, please contact Hifn customer support.
Type:
Offset
Read/Write one to clear
x‘0808’
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field Name
Reserved
Description
Bits
Reset
31:6
0
Reserved.
RING_FAIL_EN
Ring Failure Interrupt Enable
Asserts an interrupt if any of the ring oscillators are
not oscillating.
5
4
3
2
0
0
0
0
0
1
Disable ring failure interrupt
Enable ring failure interrupt
LEG2_XOR_ERR_EN
LEG1_XOR_ERR_EN
TREE_XOR_ERR_EN
Leg 2 XOR Error Interrupt Enable
Asserts an interrupt if there was an error in the Leg
2 XOR RNG logic.
0
1
Disable Leg 2 XOR error interrupt
Enable Leg 2 XOR error interrupt
Leg 1 XOR Error Interrupt Enable
Asserts an interrupt if there was an error in the Leg
1 XOR RNG logic.
0
1
Disable Leg 1 XOR error interrupt
Enable Leg 1 XOR error interrupt
Tree XOR Error Interrupt Enable
Asserts an interrupt if there was an error in the Tree
XOR RNG logic.
0
1
Disable Tree XOR error interrupt
Enable Tree XOR error interrupt
820x – Data Sheet, DS-0157-D
Page172
Hifn Confidential
EXAR [ EXAR CORPORATION ]
