5NP4G
Contents
7.5.2 Timers .................................................................................................................................. 286
7.5.2.1 Timer Interrupt Counters .............................................................................................. 287
7.6 Dispatch Unit ................................................................................................................................. 288
7.6.1 Port Configuration Memory .................................................................................................. 290
7.6.1.1 Port Configuration Memory Index Definition ................................................................. 290
7.6.2 Port Configuration Memory Contents Definition .................................................................. 291
7.6.3 Completion Unit ................................................................................................................... 292
7.7 Hardware Classifier ....................................................................................................................... 293
7.7.1 Ingress Classification ........................................................................................................... 293
7.7.1.1 Ingress Classification Input .......................................................................................... 293
7.7.1.2 Ingress Classification Output ........................................................................................ 295
7.7.2 Egress Classification ........................................................................................................... 298
7.7.2.1 Egress Classification Input ........................................................................................... 298
7.7.2.2 Egress Classification Output ........................................................................................ 299
7.7.3 Completion Unit Label Generation ...................................................................................... 299
7.8 Policy Manager ............................................................................................................................. 301
7.9 Counter Manager .......................................................................................................................... 304
7.9.1 Counter Manager Usage ..................................................................................................... 307
7.10 Semaphore Manager .................................................................................................................. 312
8. Tree Search Engine ................................................................................................ 315
8.1 Overview ....................................................................................................................................... 315
8.1.1 Addressing Control Store (CS) ............................................................................................ 315
8.1.2 D6 Control Store. ................................................................................................................. 316
8.1.3 Logical Memory Views of D6 ............................................................................................... 317
8.1.4 Control Store Use Restrictions ............................................................................................ 318
8.1.5 Object Shapes ..................................................................................................................... 318
8.1.6 Illegal Memory Access ......................................................................................................... 322
8.1.7 Memory Range Checking (Address Bounds Check) ........................................................... 322
8.2 Trees and Tree Searches ............................................................................................................. 323
8.2.1 Input Key and Color Register for FM and LPM Trees ......................................................... 324
8.2.2 Input Key and Color Register for SMT Trees ...................................................................... 324
8.2.3 Direct Table ......................................................................................................................... 325
8.2.3.1 Pattern Search Control Blocks (PSCB) ........................................................................ 325
8.2.3.2 Leaves and Compare-at-End Operation ...................................................................... 326
8.2.3.3 Cascade/Cache ............................................................................................................ 326
8.2.3.4 Cache Flag and NrPSCBs Registers ........................................................................... 326
8.2.3.5 Cache Management ..................................................................................................... 327
8.2.3.6 Search Output .............................................................................................................. 327
8.2.4 Tree Search Algorithms ....................................................................................................... 327
8.2.4.1 FM Trees ...................................................................................................................... 327
8.2.4.2 LPM Trees .................................................................................................................... 328
8.2.4.3 LPM PSCB Structure in Memory .................................................................................. 329
8.2.4.4 LPM Compact PSCB Support ...................................................................................... 329
8.2.4.5 LPM Trees with Multibit Compare ................................................................................ 331
8.2.4.6 SMT Trees .................................................................................................................... 335
8.2.4.7 Compare-at-End Operation .......................................................................................... 335
8.2.4.8 Ropes ........................................................................................................................... 338
8.2.4.9 Aging ............................................................................................................................ 339
5NP4G Network Processor, Data Sheet, DS-0125-02
January 2006
Contents
Page 7 of 607
EXAR [ EXAR CORPORATION ]
