5NP4G
Serial / Parallel Manager Interface
9. Serial / Parallel Manager Interface
Located within the Embedded Processor Complex (EPC), the Serial / Parallel Manager (SPM) Interface is a
serial interface for communication with external devices. The SPM Interface consists of a clock signal output,
a bi-directional data signal, and an interrupt input. On this interface, the 5NP4G is the master and the external
SPM module is the only slave1. The SPM Interface loads picocode, allowing management of physical layer
devices (PHYs) and access to card-based functions such as light-emitting diodes (LEDs).
The SPM Interface supports:
• An external SPM module
• Boot code load via external SPM and EEPROM
• Boot override via CABWatch interface or Boot_Picocode configuration device I/O
• Access to external PHYs, LEDs, management, and card-based functions
9.1 SPM Interface Components
Figure 9-1 shows the functional blocks of the SPM Interface. The list following the figure describes them.
Figure 9-1. SPM Interface Block Diagram
Instruction
Boot State
Memory
Machine
Parallel to
Serial
Control
External SPM Module
CAB
Interface
CAB
Boot State Machine
Starts up after reset if configured to do so by an external I/O pin (Boot_Picocode
set to 0). It selects one of two boot images (picocode loads) based on a configura-
tion flag found in the EEPROM and places the code into the instruction memory in
the EPC. Once the code is loaded, the Boot State Machine causes an interrupt that
starts up the Guided Frame Handler (GFH) thread, which executes the loaded
code.
CAB Interface
A memory mapped interface to the 5NP4G that allows the protocol processors to
access any external device, including an SPM module, external PHYs, or card
LEDs.
Parallel to Serial
Control
Converts between the internal 32-bit read/write parallel interface and the 3-bit
external bi-directional serial interface.
1.Hifn does not supply the external SPM module.
5NP4G Network Processor, Data Sheet, DS-0125-02
January 2006
Serial / Parallel Manager Interface
Page 389 of 607