5NP4G
Embedded Processor Complex
7.2.1 Core Language Processor (CLP)
Each DPPU contains two CLPs. The CLP executes the EPC’s core instruction set and controls thread swap-
ping and instruction fetching. Each CLP is a 32-bit picoprocessor consisting of:
• 16 32-bit or 32 16-bit General Purpose Registers (GPRs) per thread. (For more information, see Table 7-
1: Core Language Processor Address Map on page 200.)
• A one-cycle ALU supporting an instruction set that includes:
- Binary addition and subtraction
- Bit-wise logical AND, OR, and NOT
- Compare
- Count leading zeros
- Shift left and right Logical
- Shift right arithmetic
- Rotate Left and Right
- Bit manipulation commands: set, clear, test, and flip
- GPR transfer of Halfword to Halfword, Word to Word, and Halfword to Word with and without sign
extensions
- All instructions can be coded to run conditionally. This eliminates the need for traditional branch-and-
test coding techniques, which improves performance and reduces the size of the code. All arithmetic
and logical instructions can be coded to execute without setting ALU status flags.
• Management for handling two threads with zero overhead for context switching
• Read-only scalar registers that provide access to the following information:
- Interrupt vectors
- Timestamps
- Output of a pseudo random number generator
- Picoprocessor status
- Work queue status (such as the ingress and egress data queues)
- Configurable identifiers (such as the blade identification)
For more information, see Table 7-1: Core Language Processor Address Map on page 200.
• 16-word instruction prefetch shared by each thread
• Instruction Execution unit that executes branch instructions, instruction fetch, and coprocessor access
• Coprocessor Data Interface (CPDI) with the following features:
- Access from any byte, halfword, or word of a GPR to an array, or from an array to a GPR
- Access to coprocessor scalar registers
- Various sign, zero, and one extension formats
- Quadword transfers within the coprocessor arrays
- Quadword reset to zero of coprocessor arrays
• Coprocessor Execution Interface (CPEI) with the following features:
- Synchronous or asynchronous coprocessor operation
- Multiple coprocessor synchronization
- Synchronization and Branch-on-Coprocessor Return Code
Embedded Processor Complex
Page 198 of 607
5NP4G Network Processor, Data Sheet, DS-0125-02
January 2006
EXAR [ EXAR CORPORATION ]
