8.8 SGMII Timing
Table 8-9. SGMII Timing
Mode
SGMII
Rise Time
(max)
Fall Time
(max)
Input Signals
Output Signals
Setup
Hold
1.00 ns
Setup
Hold
1.20 ns
0.75ns
0.75ns
1.00 ns
1.20 ns
8.9 SerDes Timing
Table 8-10. SerDes Timing
Mode
Rise Time
(max)
Fall Time
(max)
Input Signals
Output Signals
Setup
Hold
1.00 ns
Setup
Hold
1.20 ns
SerDes
0.75ns
0.75ns
1.00 ns
1.20 ns
8.10 SDRAM Timing
The 4450 only supports DDR2 SDRAM. The SDRAM interface signal timing is derived from
the PLL Ref clock. The table below summarizes the timing parameters for the SDRAM
Controller. All timing is relative to the external SDRAM Clock.
Please see the 4450/8450 Hardware Design Application Note for more details on routing
guidelines and general information about the DD2 interface. The timing numbers shown in
Table 8-11 are only a subset of all the DDR2 timing requirements, but represent the most
relevant.
Table 8-11. SDRAM Interface Timing
Symbol
Tck
Parameter
Min
Max
Units
ps
Clock cycle time
Clock high level width
Clock low level width
Clock half period
Address/Ctrl Hold
Address/Ctrl setup
DQ/DM hold
5000
2250
2250
2250
800
5000
2250
2250
Tch
ps
Tcl
ps
Thp
Th
ps
ps
Ts
1000
500
ps
Tdh
Tds
ps
DQ/DM setup
500
ps
Tdqss
Tdqsq
Tqhs
Tqh
Write to first DQS
DQS-DQ skew
WL -0.25
WL+ 0.25
450
Tck
ps
DQ hold skew factor
DQ/DQS hold
550
ps
1700
ps
4450 – Data Sheet, DS-0131-06
Page77
Hifn Confidential
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