4.3 Public Key Processing
The 4450 Public Key processing includes the eSC embedded processor and efficient Public
Key acceleration hardware. To optimize the public key acceleration, the Public Key
processor is equipped with dedicated OpCode-based exponentiation hardware. The Public
Key processor operates on a batch of modular arithmetic instructions. Since each modular
arithmetic instruction (nano instruction) execution is eSC independent, the eSC is only
required to setup the Public Key engine with operands, issue instructions, and retrieve the
result upon completion of Public Key processing.
4.4 Clock Domains
The 4450 has separate clock domains for the GMAC interfaces, the internal packet
processing units, and the external SDRAM interfaces. The GMII/MII interfaces run at 125/
25/2.5 MHz (corresponding to 1G, 100M or 10M interface speeds), the packet processing
units run at 200MHz, and the SDRAM interfaces run at 200MHz.
The clock domains are controlled by a clock generation PLL, whose reference clock input is
either single-ended (prefclk) or differential (srefclk_p, srefclk_n). When in Serdes or SGMII
mode, the reference clock for the clock generation PLL must be the differential clock input
driven at a frequency of 125MHz. When the Serdes/SGMII interface is not being used, the
reference clock for the clock generation PLL is the single-ended clock input. The single-
ended PLL reference input can be either 25MHz or 125MHz, selected by the pll_mode[1]
select pin. With either input frequency, the appropriate clocks will be generated to support
10/100/1000 speeds assuming Serdes/SGMII mode is not selected. If Serdes (and/or TBI/
RTBI) mode is selected for a given interface, operation is limited to 1G speed only for that
interface.
4450 – Data Sheet, DS-0131-06
Page26
Hifn Confidential
EXAR [ EXAR CORPORATION ]
