• True Hardware Random Number Generator
2.4 Supports Multiple Host Interfaces
• Four standard RGMII/RTBI/SGMII/SERDES interfaces (The Host-side interface can
also support GMII/TBI. The four GMAC interfaces can optionally be configured for
MII mode in 10/100 applications)
• Optional Out-of-Band Control interface via RMII interface for expandability, control,
and configuration
• Compliant with IEEE 802.3 & IEEE 802.3z specifications
• Supports auto-negotiated 10/100/1000 Mbps data rates for GMII, RGMII and SGMII
Interfaces. (TBI, RTBI and SERDES interfaces only support 1Gbps)
• Supports CSMA/CD (half-duplex) and IEEE 802.3x (full-duplex) flow control
• Supports 802.3Q VLAN tag detection for received frames
• Supports 802.3 jumbo frames (9022 bytes)
• Supports 802.3z bursting (half-duplex only)
2.5 On-chip Memory
• On-chip memory used for local SPD, SAD storage and packet buffering
• Reduces cost and board space when a limited number of secure tunnels is required
2.6 Software Support
• Software Development Kit (SDK)
• IPsec and IPcomp fast-path embedded firmware provided by Hifn and bootloaded
into chip at power-up
• Optional IKE software fully integrated on chip
• Fragment reassembly (exception handling) may be performed on-chip in the eSC or
off-chip in the host, CPU, TOE, or Storage Processor
2.7 Other Features
• Supports low-cost implementations with 324-pin HSBGA package
• On-chip PLL enables flexible low-cost external clock input
• IEEE 1149.1 JTAG support
• 1.0V core power with flexible I/O voltages.
• Typical power dissipation ~2.5W
• 0.13µ process
4450 – Data Sheet, DS-0131-06
Page19
Hifn Confidential
EXAR [ EXAR CORPORATION ]
