8 PIN DIP LOW INPUT CURRENT HIGH GAIN
SPLIT DARLINGTON PHOTOCOUPLER
6N138 6N139
Pulse
Generator
Tr=5ns,
Zo=50Ω
I
F
Monitor
+5V
I
F
R
L
V
F
Vo
0.1uF
0.1uF
IF
VO
1.5V
VOL
5V
R
in
t
PHL
t
PLH
Fig. 13 Switching Time Test Circuit and Waveform
I
F
+5V
B
A
V
FF
V
F
R
L
Vo
0.1uF
CM
H
: Switch at B (IF=0mA)
CM
L
: Switch at A (IF=1.6mA)
V
CM
Fig. 14 Common Mode Transient Immunity Test Circuit and Waveform
Note:
*3 Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the
leading edge of the common mode pulse signal VCM, to assure that the output will remain in a logic high
state (i.e., VO > 2.0V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the
trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low
state (i.e., VO < 0.8V).
Everlight Electronics Co., Ltd.
Document No：DPC-0000019
7
Rev.2
http://www.everlight.com
February 23, 2009
EVERLIGHT [ EVERLIGHT ELECTRONICS CO., LTD ]
