EUP7996
Component Selection
INPUT CAPACITOR
The input capacitor should be located as close as
possible to the PVIN pin. Several recommendations
exist dependent on the application required. A typical
value recommended for AL electrolytic capacitors is
47uF. If the two supply rails (AVIN and PVIN) are
separated then the 47uF capacitor should be placed as
close to possible to PVIN rail. An additional 0.1uF
ceramic capacitor can be placed on the AVIN rail to
prevent excessive noise from coupling into the device.
OUTPUT CAPACITOR
As general recommendation, the output capacitor should
be sized above 220uF with a low ESR for SSTL
applications with DDR-SDRAM. The value of ESR
should be determined by maximum current spikes
expected from the DDR memory system to ensure V
TT
staying within +/-40mV of V
REF
. Capacitor selection can
be varied depending on the number of lines terminated
and the maximum load transient.
With motherboards and other applications where VTT is
distributed across a long plane it is advisable to use
multiple bulk capacitors. Large aluminum electrolytic
capacitors can be used for their low ESR and low cost.
Additional 0.1uF ceramic capacitor is needed for high
frequency decoupling.
When size and performance are critical, several hybrid
capacitors such OS-CON and SP that offer a large
capacitance while maintaining a low ESR are the better
solution.
PCB Layout Considerations
The EUP7996 regulator is packaged in plastic SOP-8
package. This small footprint package is unable to
convectively dissipate at high current levels. The
junction temperature should be kept well away from the
thermal shutdown temperature in normal operation. To
prevent damaging the part from exceeding the maximum
allowable junction temperature, care should be taken to
derate the part dependent on several variables: the
thickness of copper on PCB; the area of top side copper
used; and the airflow. Using large traces and more
copper on the top side of board with careful layout are
possible to reduce thermal resistance on the part.
If the large ground trace around the IC is unavailable on
top, numerous vias to connect the part and dissipate heat
to the internal ground plane will help. The vias should
be small enough to retain solder when the board is
wave- soldered.
Additional improvements can be achieved with a
constant airflow across the package.
Test Circuit
Figure 2. Load transient (+1.5A ~ –1.5A) test circuit
DS7996 Ver2.5
June.2005
9
EUTECH [ EUTECH MICROELECTRONICS INC ]
