EUP7171
Function Block Diagram
Pin Functions
VCNTL and VIN
VCNTL and VIN are the input supply pins for the
EUP7171. VIN provides the rail voltage for VOUT
generation. VCNTL is used to supply the internal
control circuitry. The limitation on input voltage
selection is that VIN must be equal to or lower than
VCNTL. For DDR I application, a separation
connection of VIN and VCNTL to 2.5V and 3.3V
respectively can achieve better output drive capability.
VREF
REFEN is an external reference input for the
EUP7171. For SSTL-2 applications, VREF should be
a 1.25V that the regulator can trace for termination
voltage VOUT. It is recommended to place a 0.01uF
to 0.1uF bypass capacitor at close to the VREF pin.
An additional function included in the VREF is an
active low shutdown. When VREF is pulled low the
VOUT output will tri-state providing a high
impedance output. A power savings advantage can be
obtained in this mode through lower quiescent
current.
VOUT
VOUT provides a regulated output for termination
bus usage. It is capable of sinking and sourcing
current while regulating the output voltage precisely
at REFEN. The regulator is designed to handle
continue current up to +/-2A with fast transient
response. If the application requires high load
current with low voltage dropped, a large output
capacitor with lower ESR(Equivalent Series
DS7171 Ver1.0 Mar. 2005
Resistance) connected at VOUT is recommended.
Thermal dissipation should be considered if the large
current continues with long duration time. If the
junction temperature exceeds the thermal shutdown
point, the VOUT will turn to tri-state.
Component Selection
In order to obtain the best performance from the
EUP7171, using lower
ESR
capacitor is necessary to
Cin and Cout for high current load. The
ESR
of the
output bulk capacitor primarily affects the capability
to deliver a current surge within a specified delta
voltage drop (ΔV) at VOUT. With a given capacitor
ESR,
the
ΔV
drop will be proportional to the load
current, and a step in voltage drop will occur.
(ΔVstep-peak = ESR * IL), the SSTL-2 spec
indicates a maximum delta voltage drop of 40mV.
A very good, low ESR electrolytic capacitor of no less
than 470uF should be placed next to the terminator,
which should be placed as possible to memory array.
It might be possible to reduce the total capacitance,
provided the performance remains stable. Examine the
behavior of the VOUT bus carefully when the system
is operating and verify that deviations in the bus
voltage do not exceed the DDR specification (+/-40
mV).
REFEN input is needed a high-frequency decoupling
capacitor (CSS). A 0.1uf ceramic capacitor should be
placed as possible to REFEN.
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EUTECH [ EUTECH MICROELECTRONICS INC ]
