EUP6514
Under Voltage Protection
output inductor and output capacitors between the
MOSEFTs and the load. Also locate the PWM
controller near by MOSFETs.
The voltage at FB pin is monitored and protected
against UV (under voltage). The UV threshold is the
FB or FBL under 80%. UV detection has 15µs
triggered delay. A hiccup restart sequence will be
operating until UV state is exited.
A multi-layer printed circuit board is recommended.
Figure 6.
PWM Layout Considerations
MOSFETs switch very fast and efficiently. The speed
with which the current transitions form one device to
another causes voltage spikes across the
interconnecting impedances and parasitic circuit
elements. The voltage spikes can degrade efficiency
and radiate noise, that results in over-voltage stress on
devices. Careful component placement layout and
printed circuit design can minimize the voltage spikes
induced in the converter. Consider, as an example, the
turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in
the upper MOSFET and is picked up by the low side
MOSFET or schottky diode. Any inductance in the
switched current path generates a large voltage spike
during the switching interval. Careful component
selections, layout of the critical components, and use
shorter and wider PCB traces help in minimizing the
magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using the EUP6514. The switching power
components are most critical because they switch
large amounts of energy, and as such, they tend to
generate equally large amounts of noise. The critical
small signal components are those connected to
sensitive nodes or those supplying critical bypass
current.
The power components and the PWM controller
should be placed firstly. Place the input capacitors,
especially the high-frequency ceramic decoupling
capacitors, close to the power switches. Place the
DS6514 Ver 1.1 Aug. 2008
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EUTECH [ EUTECH MICROELECTRONICS INC ]
