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EM6AB160WKE-5H 参数 Datasheet PDF下载

EM6AB160WKE-5H图片预览
型号: EM6AB160WKE-5H
PDF下载: 下载PDF文件 查看货源
内容描述: [32M x 16 bit DDR Synchronous DRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 62 页 / 560 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM6AB160  
EtronTech  
Table 16. Electrical Characteristics and Recommended A.C.Operating Condition  
(VDD = 2.5V ± 0.2V, TA = 0~70 °C)  
-4  
-5  
Symbol  
Parameter  
Unit Note  
Min.  
Max.  
-
Min.  
7.5  
6
Max.  
12  
CL = 2  
CL = 2.5  
CL = 3  
-
-
ns  
ns  
ns  
tCK  
tCK  
Clock cycle time  
tCK  
-
12  
4
12  
5
12  
Clock high level width  
Clock low level width  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
tCH  
tCL  
tCLMIN or  
tCHMIN  
tCLMIN or  
tCHMIN  
Clock half period  
-
-
tHP  
ns  
2
-
0.7  
0.7  
0.6  
0.7  
-
0.7  
0.7  
0.6  
0.7  
tHZ  
tLZ  
Data-out-high impedance time from CK,  
Data-out-low impedance time from CK,  
ns  
ns  
ns  
ns  
3
3
CK  
CK  
-0.7  
-0.6  
-0.7  
-0.7  
-0.6  
-0.7  
tDQSCK DQS-out access time from CK,  
CK  
tAC  
Output access time from CK,  
CK  
DQS-DQ Skew  
-
0.9  
0.4  
0.8  
0
0.4  
-
0.9  
0.4  
0.72  
0
0.4  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPRE  
tWPST  
tDQSH  
tDQSL  
tIS  
ns  
tCK  
tCK  
tCK  
ns  
tCK  
tCK  
tCK  
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
ns  
µs  
tCK  
ns  
ns  
ns  
ns  
ns  
tCK  
tCK  
Read preamble  
1.1  
1.1  
Read postamble  
0.6  
0.6  
CK to valid DQS-in  
DQS-in setup time  
1.2  
1.25  
-
-
4
5
DQS Write preamble  
DQS write postamble  
DQS in high level pulse width  
DQS in low level pulse width  
0.25  
0.4  
0.35  
0.35  
0.7  
0.7  
0.4  
0.4  
tHP - tQHS  
55  
-
0.25  
0.4  
0.35  
0.35  
0.7  
0.7  
0.4  
0.4  
tHP - tQHS  
55  
-
0.6  
0.6  
-
-
-
-
Address and Control input setup time  
Address and Control input hold time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
DQ/DQS output hold time from DQS  
Row cycle time  
-
-
6
6
-
-
tIH  
-
-
tDS  
-
-
tDH  
-
-
tQH  
-
-
tRC  
Refresh row cycle time  
70  
-
70  
-
tRFC  
tRAS  
tRCD  
tRP  
Row active time  
40  
70K  
40  
70K  
Active to Read or Write delay  
Row precharge time  
15  
-
15  
-
15  
-
15  
-
Row active to Row active delay  
Write recovery time  
8
-
10  
-
tRRD  
tWR  
12  
-
15  
-
Internal Write to Read Command Delay  
Mode register set cycle time  
Average Periodic Refresh interval  
Self refresh exit to read command delay  
2
-
2
-
tWTR  
tMRD  
tREFI  
tXSRD  
tXSNR  
tDAL  
8
-
10  
-
-
7.8  
-
7.8  
7
200  
75  
-
200  
75  
-
Self refresh exit to non-read command delay  
Auto Precharge write recovery + precharge time  
DQ and DM input pulse width  
-
-
tWR+tRP  
1.75  
2.2  
-
-
tWR+tRP  
1.75  
2.2  
-
-
-
-
-
-
tDIPW  
tIPW  
tQHS  
tDSS  
Control and Address input pulse width  
Data Hold Skew Factor  
0.5  
-
0.5  
-
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
0.2  
0.2  
0.2  
0.2  
-
-
tDSH  
tRCD or  
tRASmin  
tRCD or  
tRASmin  
Active to Autoprecharge Delay  
-
-
tRAP  
ns  
Rev.1.3  
12  
Jun. /2015  
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