EM6AB160
EtronTech
Table 17. Recommended A.C. Operating Conditions
(VDD = 2.5V ± 0.2V, TA = 0~70 °C)
Symbol
Parameter
Min.
Max.
Unit
Input High Voltage (AC)
Input Low Voltage (AC)
VIH (AC)
V
VREF + 0.31
-
VIL (AC)
VID (AC)
V
V
V
-
VREF – 0.31
VDDQ + 0.6
Input Different Voltage, CK and
inputs
CK
0.7
Input Crossing Point Voltage, CK and
inputs
VIX (AC)
CK
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note:
1) Enables on-chip refresh and address counters.
2) Min(tCL, tCH) refers to the smaller of the actual clock low time and actual clock high time as provided to the device.
3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving(HZ), or begins
driving(LZ).
4) The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on tDQSS
.
5) The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
≧
1.0V/ns.
6) For command/address and CK &
slew rate
CK
7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
8) Power-up sequence is described in Note 10
9) A.C. Test Conditions
Table 17. SSTL _2 Interface
Reference Level of Output Signals (VREF
)
0.5 * VDDQ
Reference to the Test Load
VREF+0.31 V / VREF-0.31 V
1 V/ns
Output Load
Input Signal Levels
Input Signals Slew Rate
Reference Level of Input Signals
0.5 * VDDQ
Figure 3. SSTL_2 A.C. Test Load
0.5 * VDDQ
50Ω
DQ, DQS
Z0=50Ω
30pF
Rev.1.3
13
Jun. /2015
ETRON [ ETRON TECHNOLOGY, INC. ]
