EtronTech
EM6AA320-XXMS
8Mx32 DDR SDRAM
Figure 3. Bank Activate Read or Write Command Timing
CK
tRCDRD
tRCDWR
tRAS
tRP
tRAS
WR
CA
tRP
tRC
tRRD
tRC
CMD
ACT
RD
PRE
ACT
RA
ACT
RA
PRE
BA
ACT
RA
ROW ADR Active
Percharge
A0-11
BA0-1
RA
CA
ROW ADR
Column ADR
BA
BA
BA
BA
BA
BA
BA
Bank ADR
Figure 4. Burst Stop for Read (CAS Letancy = 5, Burst Length = 4)
0
1
2
3
4
5
6
7
8
CK#
CK
CMD
RD
BST
CMD
Burst Stop for CAS Latency = 5
A0-11,
BA0-1
Valid
After 1 x CK Command can be active
1x CK
DQS
DQ
DQ0 DQ1
Figure 5. Read with Auto Precharge (CAS Letancy = 5, Burst Length = 4)
0
1
2
3
4
5
6
CK#
CK
Read with Auto Precharge
CAS Latency = 5
Bank can be Active after Auto Precharge
CMD
ACT
RDA
Valid
A0-11,
BA0-1
Valid
tRP
DQS
DQ
Begin of Auto Precharge
DQ2 DQ3
DQ0 DQ1
13
Rev 0.7
May. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
